diff -Nrcpad gcc-16-20260822/ChangeLog gcc-16-20260829/ChangeLog
*** gcc-16-20260822/ChangeLog	Sat Aug 22 22:32:05 2026
--- gcc-16-20260829/ChangeLog	Sat Aug 29 22:32:04 2026
***************
*** 1,3 ****
--- 1,8 ----
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	* MAINTAINERS: Update Michael Meissner's information.
+ 	Backported from master from 2026-08-07.1
+ 
  2026-08-07  Release Manager
  
  	* GCC 16.2.0 released.
diff -Nrcpad gcc-16-20260822/LAST_UPDATED gcc-16-20260829/LAST_UPDATED
*** gcc-16-20260822/LAST_UPDATED	Sat Aug 22 22:32:23 2026
--- gcc-16-20260829/LAST_UPDATED	Sat Aug 29 22:32:21 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-16 revision 7821eb2d69c6bab2d32d6b5d306ce35ef7666452
--- 1 ----
! Obtained from git: releases/gcc-16 revision 52db3adefd3e50d7f391a6dd77832cb9cfec71e1
diff -Nrcpad gcc-16-20260822/MAINTAINERS gcc-16-20260829/MAINTAINERS
*** gcc-16-20260822/MAINTAINERS	Sat Aug 22 22:32:05 2026
--- gcc-16-20260829/MAINTAINERS	Sat Aug 29 22:32:04 2026
*************** Richard Earnshaw
*** 36,42 ****
  Jakub Jelinek                                   <jakub@redhat.com>
  Richard Kenner                                  <kenner@nyu.edu>
  Jeff Law                                        <jeffrey.law@oss.qualcomm.com>
! Michael Meissner                                <gnu@the-meissners.org>
  Jason Merrill                                   <jason@redhat.com>
  David S. Miller                                 <davem@redhat.com>
  Joseph Myers                                    <josmyers@redhat.com>
--- 36,42 ----
  Jakub Jelinek                                   <jakub@redhat.com>
  Richard Kenner                                  <kenner@nyu.edu>
  Jeff Law                                        <jeffrey.law@oss.qualcomm.com>
! Michael Meissner                                <meissner@gcc.gnu.org>
  Jason Merrill                                   <jason@redhat.com>
  David S. Miller                                 <davem@redhat.com>
  Joseph Myers                                    <josmyers@redhat.com>
*************** riscv port              Jim Wilson
*** 116,122 ****
  rs6000/powerpc port     David Edelsohn          <dje.gcc@gmail.com>
  rs6000/powerpc port     Segher Boessenkool      <segher@kernel.crashing.org>
  rs6000/powerpc port     Kewen Lin               <linkw@gcc.gnu.org>
! rs6000 vector extns     Aldy Hernandez          <aldy@quesejoda.com>
  rx port                 Nick Clifton            <nickc@redhat.com>
  s390 port               Ulrich Weigand          <uweigand@de.ibm.com>
  s390 port               Andreas Krebbel         <krebbel@linux.ibm.com>
--- 116,122 ----
  rs6000/powerpc port     David Edelsohn          <dje.gcc@gmail.com>
  rs6000/powerpc port     Segher Boessenkool      <segher@kernel.crashing.org>
  rs6000/powerpc port     Kewen Lin               <linkw@gcc.gnu.org>
! rs6000/powerpc port     Michael Meissner        <meissner@gcc.gnu.org>
  rx port                 Nick Clifton            <nickc@redhat.com>
  s390 port               Ulrich Weigand          <uweigand@de.ibm.com>
  s390 port               Andreas Krebbel         <krebbel@linux.ibm.com>
*************** libphobos               Iain Buclaw
*** 201,207 ****
  line map                Dodji Seketeli          <dodji@redhat.com>
  soft-fp                 Joseph Myers            <josmyers@redhat.com>
  scheduler (+ haifa)     Jim Wilson              <wilson@tuliptree.org>
- scheduler (+ haifa)     Michael Meissner        <gnu@the-meissners.org>
  scheduler (+ haifa)     Jeff Law                <jeffreyalaw@gmail.com>
  scheduler (+ haifa)     Vladimir Makarov        <vmakarov@redhat.com>
  modulo-scheduler        Roman Zhuykov           <zhroma@ispras.ru>
--- 201,206 ----
*************** Bryce McKinlay                  bryce
*** 686,692 ****
  Karl Meakin                     -               <karl.meakin@arm.com>
  Adam Megacz                     -               <adam@xwt.org>
  Bingfeng Mei                    meibf           <bmei@broadcom.com>
! Michael Meissner                meissner        <gnu@the-meissners.org>
  Josef Melcr                     jmelcr          <josef.melcr@suse.com>
  Jason Merrill                   jason           <jason@redhat.com>
  Jim Meyering                    -               <jim@meyering.net>
--- 685,691 ----
  Karl Meakin                     -               <karl.meakin@arm.com>
  Adam Megacz                     -               <adam@xwt.org>
  Bingfeng Mei                    meibf           <bmei@broadcom.com>
! Michael Meissner                meissner        <meissner@gcc.gnu.org>
  Josef Melcr                     jmelcr          <josef.melcr@suse.com>
  Jason Merrill                   jason           <jason@redhat.com>
  Jim Meyering                    -               <jim@meyering.net>
diff -Nrcpad gcc-16-20260822/MD5SUMS gcc-16-20260829/MD5SUMS
*** gcc-16-20260822/MD5SUMS	Sat Aug 22 22:32:29 2026
--- gcc-16-20260829/MD5SUMS	Sat Aug 29 22:32:27 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20260822.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20260829.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** ac5a8807f431d3dab46a7425b96379e4  .gitig
*** 24,35 ****
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--- 24,35 ----
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*** 530,536 ****
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--- 530,536 ----
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*** 568,574 ****
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--- 568,574 ----
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*************** c8c9dd1eaee4ffd4d5d9f3ab70fddd4b  gcc/RE
*** 580,586 ****
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  e74733ebf762151e601c9e0aa1461a20  gcc/aclocal.m4
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! 3283dc59f72d2d6314bbbfbac1229d98  gcc/ada/ChangeLog
  c2094c0d3135f9ac89917f162046ee04  gcc/ada/ChangeLog-2001
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--- 580,586 ----
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*************** fabb943ae5026300821049a63f358453  gcc/ad
*** 761,767 ****
  3dc31e56d392ba3da0e312527adcd953  gcc/ada/eval_fat.adb
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! 3dfa27fbeea249124e1bd384e1ec62af  gcc/ada/exp_aggr.adb
  8d6933ec0ee945c50b4e8c114b1221b6  gcc/ada/exp_aggr.ads
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--- 761,767 ----
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  2a027dfad5944cc346ee7c94c022d302  gcc/ada/exp_atag.ads
*************** b218f741c2f54f950d065bb40f5125ea  gcc/co
*** 3466,3472 ****
  4d82eb0ae58ac44e02bff98ed16ac27d  gcc/common/config/frv/frv-common.cc
  5b41dfaa1b910962a78074d1e5d611d6  gcc/common/config/gcn/gcn-common.cc
  30ff9a49f51b477d26fe8159736f2269  gcc/common/config/h8300/h8300-common.cc
! f574312c1a5605d4fb4dd6510d703a54  gcc/common/config/i386/cpuinfo.h
  3ca0d2209d750e1a298b711e7b1fe2f4  gcc/common/config/i386/i386-common.cc
  976cce98e0e6b4dc4c3c50bd142ef5cd  gcc/common/config/i386/i386-cpuinfo.h
  24557722d0737993019d96d84cee0094  gcc/common/config/i386/i386-isas.h
--- 3466,3472 ----
  4d82eb0ae58ac44e02bff98ed16ac27d  gcc/common/config/frv/frv-common.cc
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*************** e3b84b8c70b76f20a6d8123da2876317  gcc/co
*** 3576,3582 ****
  88f4473ff255da227dee1dbc66c11a5f  gcc/config/aarch64/aarch64-sve-builtins.h
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! 9482a051d967c399dfed0923c294de3f  gcc/config/aarch64/aarch64-sys-regs.def
  4d85753c314f127c5c701c3fc4c29ae5  gcc/config/aarch64/aarch64-tune.md
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--- 3576,3582 ----
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*************** a003e2850cf677560132fd307ecee01f  gcc/co
*** 3871,3883 ****
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--- 3871,3883 ----
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*************** dbcdd5d37809de3b588c89731b456a95  gcc/co
*** 4237,4243 ****
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--- 4237,4243 ----
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*************** ccf120397e978f8cd4ed98cbe2c0d4f5  gcc/co
*** 5020,5026 ****
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--- 5020,5026 ----
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*************** fbba4e9f3f0e00cdc072f9a3d399d0d1  gcc/co
*** 5051,5057 ****
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--- 5051,5057 ----
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  5cb39713c38f481ef65328ccacfc067e  gcc/config/riscv/riscv-c.cc
  3b7012a7d47b9aaf163e890d3e29013e  gcc/config/riscv/riscv-cmo.def
! dfbb45804530926337bfb7741b97ad85  gcc/config/riscv/riscv-cores.def
  165a5d0020971e2616fa7c9198c56338  gcc/config/riscv/riscv-d.cc
  c5d537324bd78e2ade1cf59d04fc1f54  gcc/config/riscv/riscv-d.h
  6078aa631d1c71fd215d51e4edcec963  gcc/config/riscv/riscv-ext-andes.def
*************** e8af52b8a6f7085bfb664f79b36b11ad  gcc/co
*** 5068,5074 ****
  70f0932c77decbbcedce26f2f38b3a3e  gcc/config/riscv/riscv-ftypes.def
  6fdf4beed9fb8574216b376cd1779eba  gcc/config/riscv/riscv-modes.def
  7e168ec0afa9d2e5b09b26f2c4c0b9cf  gcc/config/riscv/riscv-opt-popretz.cc
! 82f8cdbc37627ec1514ac6f802e92fcd  gcc/config/riscv/riscv-opts.h
  b8f6d36a9d7d3ef28a80c20bec990411  gcc/config/riscv/riscv-passes.def
  8fcaaf812bb193e0fad76d6b5f82f2af  gcc/config/riscv/riscv-profiles.def
  099a75556ecb2bf7380158582cae2022  gcc/config/riscv/riscv-protos.h
--- 5068,5074 ----
  70f0932c77decbbcedce26f2f38b3a3e  gcc/config/riscv/riscv-ftypes.def
  6fdf4beed9fb8574216b376cd1779eba  gcc/config/riscv/riscv-modes.def
  7e168ec0afa9d2e5b09b26f2c4c0b9cf  gcc/config/riscv/riscv-opt-popretz.cc
! 0cf7e7ae52346622fd0057b1356ad7cd  gcc/config/riscv/riscv-opts.h
  b8f6d36a9d7d3ef28a80c20bec990411  gcc/config/riscv/riscv-passes.def
  8fcaaf812bb193e0fad76d6b5f82f2af  gcc/config/riscv/riscv-profiles.def
  099a75556ecb2bf7380158582cae2022  gcc/config/riscv/riscv-protos.h
*************** b65281b3d979c9c774d30d65281a07ab  gcc/co
*** 5099,5105 ****
  85dee253312a7f85a1d4f8554a601105  gcc/config/riscv/riscv-zicfilp.cc
  ee99c42de7ee8558b649c3dfbe62f19a  gcc/config/riscv/riscv.cc
  e05413eb674ee60a2093593f30382882  gcc/config/riscv/riscv.h
! 65c5422452e0d68e0c39c06164c8e7f7  gcc/config/riscv/riscv.md
  c721fa1217a74f723ccf84813f721944  gcc/config/riscv/riscv.opt
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  fab1eef01628cdb4fc6f7a48edf3ff51  gcc/config/riscv/riscv_bitmanip.h
--- 5099,5105 ----
  85dee253312a7f85a1d4f8554a601105  gcc/config/riscv/riscv-zicfilp.cc
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  e05413eb674ee60a2093593f30382882  gcc/config/riscv/riscv.h
! c5d741f7a62a3d899b36734241715cd7  gcc/config/riscv/riscv.md
  c721fa1217a74f723ccf84813f721944  gcc/config/riscv/riscv.opt
  5347f266751815cd3cb80c0de985c3b8  gcc/config/riscv/riscv.opt.urls
  fab1eef01628cdb4fc6f7a48edf3ff51  gcc/config/riscv/riscv_bitmanip.h
*************** fe202105dd9e81b9ce8fdcc11d52c294  gcc/co
*** 5132,5138 ****
  bcf728ad2379630774fd5bb529d4ee86  gcc/config/riscv/thead-vector.md
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! a95321fbec5a4da32a9ee8145b8b0c6d  gcc/config/riscv/tt-ascalon-d8.md
  dcbac9d3c6831ff1cd18effca9c7bb28  gcc/config/riscv/vector-bfloat16.md
  1efc7e76b1f8a6c41de01fba7e0d33b9  gcc/config/riscv/vector-crypto.md
  604805ea8530b1a6391150e8388a63fb  gcc/config/riscv/vector-iterators.md
--- 5132,5138 ----
  bcf728ad2379630774fd5bb529d4ee86  gcc/config/riscv/thead-vector.md
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  03801432922f48ba0343aa17544bdba7  gcc/config/riscv/thead.md
! b4354f6efc747a041e9278fc24e89024  gcc/config/riscv/tt-ascalon-d8.md
  dcbac9d3c6831ff1cd18effca9c7bb28  gcc/config/riscv/vector-bfloat16.md
  1efc7e76b1f8a6c41de01fba7e0d33b9  gcc/config/riscv/vector-crypto.md
  604805ea8530b1a6391150e8388a63fb  gcc/config/riscv/vector-iterators.md
*************** e2851e68e3cf5a2530acf22e54486538  gcc/co
*** 5216,5222 ****
  48b677adc79f0805eb737ff06c673161  gcc/config/rs6000/htmxlintrin.h
  a99d948e8d06e7754418348c976d8deb  gcc/config/rs6000/immintrin.h
  e4b02417cb4df9d5a76c80b1ff2a9f74  gcc/config/rs6000/linux.h
! 0a507b8eec6391ca9fa75de53d805c39  gcc/config/rs6000/linux64.h
  235e303765b8162269663d6af8853c33  gcc/config/rs6000/linux64.opt
  29455a0f359b87f59b8bcfc5bf1e6d61  gcc/config/rs6000/linux64.opt.urls
  15a29c14042c17704cd788e9ec97f8b3  gcc/config/rs6000/linuxaltivec.h
--- 5216,5222 ----
  48b677adc79f0805eb737ff06c673161  gcc/config/rs6000/htmxlintrin.h
  a99d948e8d06e7754418348c976d8deb  gcc/config/rs6000/immintrin.h
  e4b02417cb4df9d5a76c80b1ff2a9f74  gcc/config/rs6000/linux.h
! e69deff976bf39fefcc8dcba890026ac  gcc/config/rs6000/linux64.h
  235e303765b8162269663d6af8853c33  gcc/config/rs6000/linux64.opt
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  15a29c14042c17704cd788e9ec97f8b3  gcc/config/rs6000/linuxaltivec.h
*************** db237fc1717a4075e7b9480205a32fd5  gcc/co
*** 5248,5254 ****
  a279505199952377f52557bce5be1325  gcc/config/rs6000/rs6000-builtins.def
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  7c9a1176a2e08f0e5427b62d9b9742e8  gcc/config/rs6000/rs6000-call.cc
! 52e2359f2b2a12d4d3f78e6f22da4e2c  gcc/config/rs6000/rs6000-cpus.def
  7b860836fdc33cdfdd29f6348a553096  gcc/config/rs6000/rs6000-d.cc
  1ac6ae1e7d6d83d76667769f7166b9a7  gcc/config/rs6000/rs6000-d.h
  33aadbc7a022914894554e071177e0ce  gcc/config/rs6000/rs6000-gen-builtins.cc
--- 5248,5254 ----
  a279505199952377f52557bce5be1325  gcc/config/rs6000/rs6000-builtins.def
  577fc739593a5c933b13e4dc37e2c774  gcc/config/rs6000/rs6000-c.cc
  7c9a1176a2e08f0e5427b62d9b9742e8  gcc/config/rs6000/rs6000-call.cc
! e13b19871c269e71cdff2581ed1c5a9a  gcc/config/rs6000/rs6000-cpus.def
  7b860836fdc33cdfdd29f6348a553096  gcc/config/rs6000/rs6000-d.cc
  1ac6ae1e7d6d83d76667769f7166b9a7  gcc/config/rs6000/rs6000-d.h
  33aadbc7a022914894554e071177e0ce  gcc/config/rs6000/rs6000-gen-builtins.cc
*************** da37007432adac35e44d7592e307e64a  gcc/co
*** 5265,5273 ****
  9e39e759376eb97f2a56ebfc28c8d149  gcc/config/rs6000/rs6000-string.cc
  835f22c956cc4deb83970ee9a9b5b79b  gcc/config/rs6000/rs6000-tables.opt
  ce8de9a27f36b759a69194616c02eb38  gcc/config/rs6000/rs6000-tables.opt.urls
! a02adfdff283fa670da666e9c2f3bb86  gcc/config/rs6000/rs6000.cc
  3dbc07b9152fd321bc08daad634f9dd2  gcc/config/rs6000/rs6000.h
! 1d473c940c2d61534db3ed605b4411eb  gcc/config/rs6000/rs6000.md
  e9eda0c22b5fe43eacbc84048e8c92b0  gcc/config/rs6000/rs6000.opt
  80708ca71755b0d8d354f113f0617617  gcc/config/rs6000/rs6000.opt.urls
  89d4cadf8216efa86b72204e660cc4b0  gcc/config/rs6000/rs64.md
--- 5265,5273 ----
  9e39e759376eb97f2a56ebfc28c8d149  gcc/config/rs6000/rs6000-string.cc
  835f22c956cc4deb83970ee9a9b5b79b  gcc/config/rs6000/rs6000-tables.opt
  ce8de9a27f36b759a69194616c02eb38  gcc/config/rs6000/rs6000-tables.opt.urls
! 998517f1f2a0421b1515fb25e55c3332  gcc/config/rs6000/rs6000.cc
  3dbc07b9152fd321bc08daad634f9dd2  gcc/config/rs6000/rs6000.h
! 4575d57ccfdb4a494b969c97442f8f9d  gcc/config/rs6000/rs6000.md
  e9eda0c22b5fe43eacbc84048e8c92b0  gcc/config/rs6000/rs6000.opt
  80708ca71755b0d8d354f113f0617617  gcc/config/rs6000/rs6000.opt.urls
  89d4cadf8216efa86b72204e660cc4b0  gcc/config/rs6000/rs64.md
*************** f11925c88524d2fd457bf77944da1302  gcc/co
*** 5307,5313 ****
  da79297ad0c4c71553a67c1c8659d7f0  gcc/config/rs6000/tmmintrin.h
  88417b4d808d053378108ca755b5e5ce  gcc/config/rs6000/vec_types.h
  d25d99ecfc5b7d30303b228b0b6b2b9d  gcc/config/rs6000/vector.md
! ece432c07c3bfc0874829e08e4c1746b  gcc/config/rs6000/vsx.md
  e01b246a8cdac36ad716112dbba238f9  gcc/config/rs6000/vxworks.h
  879b35d5e026800c40c13e663df8c5f9  gcc/config/rs6000/vxworksae.h
  aa45c89828fac6551d8d57309cf26ec0  gcc/config/rs6000/vxworksmils.h
--- 5307,5313 ----
  da79297ad0c4c71553a67c1c8659d7f0  gcc/config/rs6000/tmmintrin.h
  88417b4d808d053378108ca755b5e5ce  gcc/config/rs6000/vec_types.h
  d25d99ecfc5b7d30303b228b0b6b2b9d  gcc/config/rs6000/vector.md
! 1a54ef4b62dc1d2504bc4504c8938048  gcc/config/rs6000/vsx.md
  e01b246a8cdac36ad716112dbba238f9  gcc/config/rs6000/vxworks.h
  879b35d5e026800c40c13e663df8c5f9  gcc/config/rs6000/vxworksae.h
  aa45c89828fac6551d8d57309cf26ec0  gcc/config/rs6000/vxworksmils.h
*************** c5ad0142a191862e3e81ecd3573754b3  gcc/co
*** 5646,5652 ****
  55a33ae415bde0fd2e36ba584894e50b  gcc/coroutine-passes.cc
  c10700723a41c720aada0096f369147e  gcc/coverage.cc
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! 3735366839c15dc03354fd11a07fd41d  gcc/cp/ChangeLog
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  7cbd106e10a0ba7c052bee3fe20671c2  gcc/cp/ChangeLog-1994
  3b1e3ed23ad4363f75e6fd2fbb583dee  gcc/cp/ChangeLog-1995
--- 5646,5652 ----
  55a33ae415bde0fd2e36ba584894e50b  gcc/coroutine-passes.cc
  c10700723a41c720aada0096f369147e  gcc/coverage.cc
  d27317cee558d7c78afbdb6529e36649  gcc/coverage.h
! 5dabd309893938a08b6f7314d9ca4f0f  gcc/cp/ChangeLog
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  7cbd106e10a0ba7c052bee3fe20671c2  gcc/cp/ChangeLog-1994
  3b1e3ed23ad4363f75e6fd2fbb583dee  gcc/cp/ChangeLog-1995
*************** eba8d8a1725223519fba5d4d69afd5c9  gcc/cp
*** 5701,5707 ****
  370b42bcdf211125186c37665052c30c  gcc/cp/cp-objcp-common.h
  ffdd05782c93c0567486bb7ed7eee65a  gcc/cp/cp-trait.def
  bc9b29434f2e35fa68caf656161b5c0f  gcc/cp/cp-tree.def
! 579937ba14b29921d3c910c10c8ac3c6  gcc/cp/cp-tree.h
  13d136a72a2aff80be380103d1c27ed5  gcc/cp/cp-ubsan.cc
  0f660920514d4f51007f6841a25e3af6  gcc/cp/cvt.cc
  f067718cf3d629084d8347c4e017afd4  gcc/cp/cxx-pretty-print.cc
--- 5701,5707 ----
  370b42bcdf211125186c37665052c30c  gcc/cp/cp-objcp-common.h
  ffdd05782c93c0567486bb7ed7eee65a  gcc/cp/cp-trait.def
  bc9b29434f2e35fa68caf656161b5c0f  gcc/cp/cp-tree.def
! 9e17c7be98549b9075b48e0d979104ed  gcc/cp/cp-tree.h
  13d136a72a2aff80be380103d1c27ed5  gcc/cp/cp-ubsan.cc
  0f660920514d4f51007f6841a25e3af6  gcc/cp/cvt.cc
  f067718cf3d629084d8347c4e017afd4  gcc/cp/cxx-pretty-print.cc
*************** b98d31c57aa038618db60991b17e0d35  gcc/cp
*** 5736,5745 ****
  9efebf39da56d681d4405dfb9e55e3f5  gcc/cp/optimize.cc
  77bf772b9207f2cd8ad20cb922ad4b9b  gcc/cp/parser.cc
  7973a34c47e3d3c580832655a3a5c3c2  gcc/cp/parser.h
! 1295dc1ecc7ca8863a6434871b9e6449  gcc/cp/pt.cc
  25322928eaff39cf167372554c639e02  gcc/cp/ptree.cc
  2cbf7a5ccd915a7df00ff5a38701f81d  gcc/cp/reflect.cc
! 6ae3f1ff3ba804579da14445501f9181  gcc/cp/rtti.cc
  ed044462caa5bbab93e33fd297bc5d7c  gcc/cp/search.cc
  7dba5fdda2dc085d8a73f2ce4a34c24d  gcc/cp/semantics.cc
  64c36b2ea66c9f8f477b19d24e06a2cb  gcc/cp/std-name-hint.gperf
--- 5736,5745 ----
  9efebf39da56d681d4405dfb9e55e3f5  gcc/cp/optimize.cc
  77bf772b9207f2cd8ad20cb922ad4b9b  gcc/cp/parser.cc
  7973a34c47e3d3c580832655a3a5c3c2  gcc/cp/parser.h
! 9795941fc1dab55be1e11f791e035b0c  gcc/cp/pt.cc
  25322928eaff39cf167372554c639e02  gcc/cp/ptree.cc
  2cbf7a5ccd915a7df00ff5a38701f81d  gcc/cp/reflect.cc
! ceb9e88bb8dfe59c2867ce417fe654b1  gcc/cp/rtti.cc
  ed044462caa5bbab93e33fd297bc5d7c  gcc/cp/search.cc
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  64c36b2ea66c9f8f477b19d24e06a2cb  gcc/cp/std-name-hint.gperf
*************** c2fc9f8e6a1cb39a7237e4ac3d7fcd7f  gcc/do
*** 6194,6200 ****
  b1b6d8120056485e6de69be9493a2129  gcc/doc/lto.texi
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  f7e932ab983b28cd4bef523021fa9eb0  gcc/doc/match-and-simplify.texi
! 566380e04638b34677ce631ce33c0147  gcc/doc/md.texi
  afaf0b9b413500a77920c3963dcd3978  gcc/doc/objc.texi
  79e8babebb4a40553fc011874ac21cbb  gcc/doc/optinfo.texi
  3abb75ff788f5434702f351bf7a279c9  gcc/doc/options.texi
--- 6194,6200 ----
  b1b6d8120056485e6de69be9493a2129  gcc/doc/lto.texi
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  f7e932ab983b28cd4bef523021fa9eb0  gcc/doc/match-and-simplify.texi
! 3cb27b97054309259cf38d45cac016fe  gcc/doc/md.texi
  afaf0b9b413500a77920c3963dcd3978  gcc/doc/objc.texi
  79e8babebb4a40553fc011874ac21cbb  gcc/doc/optinfo.texi
  3abb75ff788f5434702f351bf7a279c9  gcc/doc/options.texi
*************** e54937e427a2584ac4045286c725fab1  gcc/do
*** 6204,6211 ****
  88abde052db83cafaf5aaa6be0471613  gcc/doc/poly-int.texi
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  1b0bb6e47b9321945dac2c2eb8b7c12b  gcc/doc/riscv-ext.texi
! 2d4ffd79938427c5ab83641203460665  gcc/doc/riscv-mcpu.texi
! f9e8c3f3f521ccb531572ed4189b13b6  gcc/doc/riscv-mtune.texi
  ee1dc9bba1241ba6755d90ce32847e63  gcc/doc/rtl.texi
  b12261ad56bcabd07b4a1b739f271527  gcc/doc/service.texi
  628720c1a9a600c7e6ef8c77ada1da6e  gcc/doc/sourcebuild.texi
--- 6204,6211 ----
  88abde052db83cafaf5aaa6be0471613  gcc/doc/poly-int.texi
  213ccf5a355e5d07fc0dcef29825d6dd  gcc/doc/portability.texi
  1b0bb6e47b9321945dac2c2eb8b7c12b  gcc/doc/riscv-ext.texi
! 8f27e7b7178e710ac90cea24742a19bb  gcc/doc/riscv-mcpu.texi
! b2584a476432ce55953f2e7862d4901e  gcc/doc/riscv-mtune.texi
  ee1dc9bba1241ba6755d90ce32847e63  gcc/doc/rtl.texi
  b12261ad56bcabd07b4a1b739f271527  gcc/doc/service.texi
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*************** ae7077f641ec004f4380dcc8efac92b6  gcc/ex
*** 6254,6260 ****
  2431f17e1f416ef0b9c38b1b975942a4  gcc/expmed.h
  eb75df114e69863f6370174248bbfadd  gcc/expr.cc
  54b30ae6372ded76e375ade2621552a1  gcc/expr.h
! 8cca7ee32636f4556dceffe46dc6c948  gcc/ext-dce.cc
  8ca3dbbcb4ffeb7bd2c8f46140869732  gcc/fibonacci_heap.cc
  3c351443d52500c559f1f91eb65b96c2  gcc/fibonacci_heap.h
  e0210f6d49bd9ceab84ba5169fbcfc99  gcc/file-find.cc
--- 6254,6260 ----
  2431f17e1f416ef0b9c38b1b975942a4  gcc/expmed.h
  eb75df114e69863f6370174248bbfadd  gcc/expr.cc
  54b30ae6372ded76e375ade2621552a1  gcc/expr.h
! 0680e8718a89d4db06b6ff35150f139e  gcc/ext-dce.cc
  8ca3dbbcb4ffeb7bd2c8f46140869732  gcc/fibonacci_heap.cc
  3c351443d52500c559f1f91eb65b96c2  gcc/fibonacci_heap.h
  e0210f6d49bd9ceab84ba5169fbcfc99  gcc/file-find.cc
*************** f80b38c70a85f9aeae9688b937b028ba  gcc/fi
*** 6271,6277 ****
  50b999b375e3a5a95a002f592e6d4514  gcc/fold-const.cc
  0ec02a37dbbe9cb267f0ea1263085ed3  gcc/fold-const.h
  a0df3d274ac009d203209a191738cec6  gcc/fold-mem-offsets.cc
! 0f50cb1fe9965d66d9f832d94ef64f43  gcc/fortran/ChangeLog
  083c53fadafdcf3be46713838a51e36c  gcc/fortran/ChangeLog-2002
  2a4ca18d211fb2603139354fd16398ed  gcc/fortran/ChangeLog-2003
  e7462609ebd0dd7c874e0fc00e2833aa  gcc/fortran/ChangeLog-2004
--- 6271,6277 ----
  50b999b375e3a5a95a002f592e6d4514  gcc/fold-const.cc
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  a0df3d274ac009d203209a191738cec6  gcc/fold-mem-offsets.cc
! 4576f6ee6007212e960a416d3ef365fc  gcc/fortran/ChangeLog
  083c53fadafdcf3be46713838a51e36c  gcc/fortran/ChangeLog-2002
  2a4ca18d211fb2603139354fd16398ed  gcc/fortran/ChangeLog-2003
  e7462609ebd0dd7c874e0fc00e2833aa  gcc/fortran/ChangeLog-2004
*************** f7735c64af748cdef5caffae58a94749  gcc/fo
*** 6345,6351 ****
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--- 6345,6351 ----
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*************** e23f6eefa51bb3b4caa3d75c0409cfcd  gcc/fo
*** 6359,6365 ****
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*************** bd823ebd6a057aabd7d4978826fbcfcc  gcc/fo
*** 6369,6375 ****
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*************** e8ef831ecab58724c781ef6c239eb959  gcc/gi
*** 6463,6469 ****
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--- 6463,6469 ----
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*************** b106a08a1793a5495dd87c412456484b  gcc/mc
*** 7893,7899 ****
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*************** f24751f278bee1ac8dc861467d9f96a3  gcc/ta
*** 8726,8732 ****
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*************** b040bc0531aab955a851fcd673e14e10  gcc/te
*** 35308,35313 ****
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*************** f93ef0cccc28030d91ef7db3de43152e  gcc/te
*** 52484,52490 ****
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*************** e6132b99fe49e5ef626b8a5c49e9670a  gcc/te
*** 62801,62807 ****
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*************** f1a49246f84d8fbab3d2b6aa5c89949e  gcc/te
*** 67722,67728 ****
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*************** ae7dd7b535828dd877ea453ce08b1b4b  gcc/te
*** 67730,67736 ****
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*** 69091,69096 ****
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*** 83428,83433 ****
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*** 85852,85857 ****
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*** 90791,90796 ****
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*** 96789,96794 ****
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*** 97300,97306 ****
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  32f9089a1eee35a3cb0ee86636d8d338  libstdc++-v3/include/std/span
! 6774992a5590ecabdb3043f103bc746e  libstdc++-v3/include/std/spanstream
  f00ff992c96a4a6422d964aad9315664  libstdc++-v3/include/std/sstream
  f5a5ebc7b6133572f8f361cde93ec52f  libstdc++-v3/include/std/stack
  11dbc7eaf7ffced493f65f6bc3b423b1  libstdc++-v3/include/std/stacktrace
*************** f6c79e469ea2b0dddd1990749fa4b787  libstd
*** 155638,155643 ****
--- 155661,155667 ----
  1fcb896c44256929a07977ca21fe5196  libstdc++-v3/testsuite/27_io/rvalue_streams-2.cc
  37900198219b3bf746a84814e92c58b9  libstdc++-v3/testsuite/27_io/rvalue_streams.cc
  9f91196bd2ee848a8c2cfc4258d112cb  libstdc++-v3/testsuite/27_io/spanstream/1.cc
+ 3594f52a64f56373d233b505e211d1ba  libstdc++-v3/testsuite/27_io/spanstream/127006.cc
  d8cec34c2a6b668a6dc232e2f6df1ff5  libstdc++-v3/testsuite/27_io/spanstream/2.cc
  33aa6ce2c2e3d3959e5a01a4971407e1  libstdc++-v3/testsuite/27_io/spanstream/version.cc
  0289439f25a083a7baf572a21ffb21b6  libstdc++-v3/testsuite/27_io/types/1.cc
diff -Nrcpad gcc-16-20260822/gcc/ChangeLog gcc-16-20260829/gcc/ChangeLog
*** gcc-16-20260822/gcc/ChangeLog	Sat Aug 22 22:32:06 2026
--- gcc-16-20260829/gcc/ChangeLog	Sat Aug 29 22:32:05 2026
***************
*** 1,3 ****
--- 1,203 ----
+ 2026-08-28  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-08-28  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/127105
+ 	* tree-vect-slp.cc (vect_analyze_slp_reduc_chain): Access
+ 	scalar_stmts[0] only after we determined it exists.
+ 
+ 2026-08-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-08-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR tree-optimization/127100
+ 	* doc/md.texi (vec_mask_len_load_lanes@var{m}@var{n}): Use
+ 	operand4 - operand5 rather than operand4 + operand5.
+ 	(vec_mask_len_store_lanes@var{m}@var{n}): Use
+ 	operand3 - operand4 rather than operand3 + operand4.
+ 	(mask_len_gather_load@var{m}@var{n}): Use operand 7 - operand 8
+ 	rather than operand 7 + operand 8.
+ 	(mask_len_strided_load@var{m}): Use operand 4 - operand 5 rather
+ 	than operand 4 + operand 5.
+ 	(mask_len_scatter_store@var{m}@var{n}): Use operand 6 - operand 7
+ 	rather than operand 6 + operand 7.
+ 	(mask_len_strided_store@var{m}): Use operand 4 - operand 5 rather
+ 	than operand 4 + operand 5.
+ 	(len_load_@var{m}): Use operand 3 - operand 4 rather than
+ 	operand 3 + operand 4.
+ 	(len_store_@var{m}): Use operand 2 - operand 3 rather than
+ 	operand 2 + operand 3.
+ 	(mask_len_load@var{m}@var{n}): Use operand 4 - operand 5 rather
+ 	than operand 3 + operand 4 or operand 4 + operand 5.  Use
+ 	Operand 5 rather than Operand 4 when talking about bias QI mode.
+ 	(mask_len_store@var{m}@var{n}): Use operand 3 - operand 4 rather
+ 	than operand 3 + operand 4 or operand 2 + operand 4.
+ 	(cond_len_neg@var{mode}): Use operand 4 - operand 5 rather than
+ 	operand 4 + operand 5.  Use ops[4] - ops[5] rather than
+ 	ops[4] + ops[5].
+ 	(cond_len_add@var{mode}): Use operand 5 - operand 6 rather than
+ 	operand 5 + operand 6.  Use ops[5] - ops[6] rather than
+ 	ops[5] + ops[6].
+ 	(cond_len_fma@var{mode}): Use ops[6] - ops[7] rather than
+ 	ops[6] + ops[7].
+ 	* gimple-fold.cc (partial_load_store_mask_state): Compute wlen
+ 	as wi::to_poly_widest (len) - wi::to_widest (bias) rather than
+ 	wi::to_poly_widest (len) + wi::to_widest (bias).
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/120681
+ 	* config/rs6000/linux64.h (PCREL_SUPPORTED_BY_OS): Allow large
+ 	code model as well as medium code model.
+ 	* config/rs6000/rs6000.cc (rs6000_option_override_internal):
+ 	Likewise.
+ 	(rs6000_elf_declare_function_name): Don't create the
+ 	local/non-local labels for large code model if we are using
+ 	PC-relative addressing.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/120528
+ 	* config/rs6000/rs6000.md (zero_extend??ti2 peephole2): Add a
+ 	peephole2 to simplify zero extending a QI/HI/SI/DImode value in
+ 	memory to a TImode target in a vector register to use the
+ 	LXVR{B,H,W,D}X instructins.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/99293
+ 	* config/rs6000/vsx.md (vsx_splat_extract_<mode>): New insn.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/117487
+ 	* config/rs6000/vsx.md (SFmode logical peephoole): Update comments in
+ 	the original code that supports power8.
+ 	(SFBOOL2_*): New constants.
+ 	(power9/power10 define_peephol2): Add a new define_peephole2 to optimize
+ 	float and logical operations on power9/power10/power11 similar to the
+ 	optimiztion that is done on power8.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	* config/rs6000/rs6000-cpus.def (FUTURE_MASKS_SERVER): Enable using load
+ 	vector pair and store vector pair instructions for memory and string
+ 	built-in functions.
+ 	(POWERPC_MASKS): Make -mblock-ops-vector-pair an option that is set by
+ 	the -mcpu=<xxx> command line option.
+ 	* config/rs6000/rs6000.cc (rs6000_machine_from_flags): Disable
+ 	-mblock-ops-vector-pair from influencing .machine selection.
+ 
+ 2026-08-26  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/125984
+ 	* tree-dfa.cc (get_ref_base_and_extent) <ARRAY_REF>: Use the range
+ 	of the difference between the index expression and the low bound,
+ 	instead of that of the index expression itself, to constrain the
+ 	maximum size of the access.
+ 
+ 2026-08-26  Dipesh Sharma  <Dipesh.Sharma@amd.com>
+ 
+ 	Backported from master:
+ 	2026-08-25  Dipesh Sharma  <Dipesh.Sharma@amd.com>
+ 
+ 	* common/config/i386/cpuinfo.h (get_available_features): Detect AVX512BMM from
+ 	extended features instead of standard leaf.
+ 	* config/i386/cpuid.h (bit_AVX512BMM): Move to extended features
+ 	section.
+ 
+ 2026-08-25  Alice Carlotti  <alice.carlotti@arm.com>
+ 
+ 	* config/aarch64/aarch64-sys-regs.def: Sync from Binutils.
+ 
+ 2026-08-25  Josef Melcr  <josef.melcr@suse.com>
+ 
+ 	Backported from master:
+ 	2026-08-25  Josef Melcr  <josef.melcr@suse.com>
+ 
+ 	PR ipa/127023
+ 	* multiple_target.cc (create_dispatcher_calls): Use the call
+ 	statement variant of create_reference.
+ 
+ 2026-08-24  Peter Bergner  <bergner@tenstorrent.com>
+ 
+ 	Backported from master:
+ 	2026-08-13  Peter Bergner  <bergner@tenstorrent.com>
+ 
+ 	* config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-xg.
+ 	(RISCV_CORE): Likewise.
+ 	* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
+ 	Add tt_ascalon_xg.
+ 	* config/riscv/riscv.md (tune): Likewise.
+ 	* config/riscv/tt-ascalon-d8.md (asc-xg-fp64-vec0, asc-xg-fp64-vec1):
+ 	New define_cpu_unit.
+ 	(tt_ascalon_xg_fp64_vec): New define_reservation.
+ 	(tt_ascalon_d8_int_load, tt_ascalon_d8_alu, tt_ascalon_d8_sfb,
+ 	tt_ascalon_d8_branch, tt_ascalon_d8_float_move, tt_ascalon_d8_fcvt,
+ 	tt_ascalon_d8_fcmp, tt_ascalon_d8_imul, tt_ascalon_d8_idiv,
+ 	tt_ascalon_d8_fadd, tt_ascalon_d8_mul, tt_ascalon_d8_float_fma,
+ 	tt_ascalon_d8_float_div_half, tt_ascalon_d8_float_div_single,
+ 	tt_ascalon_d8_float_div_double, tt_ascalon_d8_popcount,
+ 	tt_ascalon_d8_vec_load, tt_ascalon_d8_vec_store,
+ 	tt_ascalon_d8_vec_load_strided, tt_ascalon_d8_vec_store_strided,
+ 	tt_ascalon_d8_vec_load_indexed, tt_ascalon_d8_vec_store_indexed,
+ 	tt_ascalon_d8_vec_loadstore_seg, tt_ascalon_d8_vec_alu_1,
+ 	tt_ascalon_d8_vec_alu_2, tt_ascalon_d8_vec_alu_3,
+ 	tt_ascalon_d8_vec_alu_4, tt_ascalon_d8_vec_imul, tt_ascalon_d8_vec_pop,
+ 	tt_ascalon_d8_vec_crypto_aes, tt_ascalon_d8_vec_crypto_sha,
+ 	tt_ascalon_d8_vec_perm_1, tt_ascalon_d8_vec_perm_3,
+ 	tt_ascalon_d8_vec_perm_4, tt_ascalon_d8_vec_reduction,
+ 	tt_ascalon_d8_vec_ordered_reduction, tt_ascalon_d8_vec_idiv_byte,
+ 	tt_ascalon_d8_vec_idiv_half, tt_ascalon_d8_vec_idiv_single,
+ 	tt_ascalon_d8_vec_idiv_double, tt_ascalon_d8_vec_float_divsqrt_half,
+ 	tt_ascalon_d8_vec_float_divsqrt_single,
+ 	tt_ascalon_d8_vec_float_divsqrt_double, tt_ascalon_d8_vec_mask,
+ 	tt_ascalon_d8_vec_vesetvl, tt_ascalon_d8_vec_setrm,
+ 	tt_ascalon_d8_vec_readlen, tt_ascalon_d8_vec_unknown):
+ 	Use tt_ascalon_xg.
+ 	(tt_ascalon_d8_vec_fcmp, tt_ascalon_d8_vec_fadd,
+ 	tt_ascalon_d8_vec_fmul): Disable vector instructions that produce FP64
+ 	output values when tuning for tt_ascalon_xg.
+ 	(tt_ascalon_xg_fp64_vec_insns): New define_insn_reservation.
+ 	* doc/riscv-mcpu.texi: Regenerate.
+ 	* doc/riscv-mtune.texi: Likewise.
+ 
+ 2026-08-24  Jin Ma  <jinma@linux.alibaba.com>
+ 
+ 	Backported from master:
+ 	2026-08-21  Jin Ma  <jinma@linux.alibaba.com>
+ 
+ 	PR target/126873
+ 	* config/riscv/autovec.md (vec_set<mode>): Zero-extend a
+ 	sub-Pmode index to Pmode.
+ 	(vec_extract<mode><vel>): Likewise.
+ 
+ 2026-08-24  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-08-14  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/126426
+ 	* ext-dce.cc (carry_backpropagate): Return a conservatively
+ 	correct mask when presented with vector modes.
+ 	(ext_dce_process_uses): Don't use GET_MODE_INNER, we need to
+ 	know the full extent of the bits for vector and complex modes.
+ 
+ 2026-08-24  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-08-23  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/127004
+ 	* config/avr/avr-passes.cc (rtl-iter.h): Include.
+ 	(insninfo_t::scratch_mask): New method.
+ 	(optimize_data_t::try_split_ldi): Use it for ignore_mask.
+ 	(optimize_data_t::try_split_any): Same.
+ 	(optimize_data_t::emit_sequence): Dump ignore_mask prior to
+ 	calling fatal_insn.
+ 
  2026-08-20  Pietro Monteiro  <pietro@sociotechnical.xyz>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260822/gcc/DATESTAMP gcc-16-20260829/gcc/DATESTAMP
*** gcc-16-20260822/gcc/DATESTAMP	Sat Aug 22 22:32:06 2026
--- gcc-16-20260829/gcc/DATESTAMP	Sat Aug 29 22:32:05 2026
***************
*** 1 ****
! 20260822
--- 1 ----
! 20260829
diff -Nrcpad gcc-16-20260822/gcc/ada/ChangeLog gcc-16-20260829/gcc/ada/ChangeLog
*** gcc-16-20260822/gcc/ada/ChangeLog	Sat Aug 22 22:32:06 2026
--- gcc-16-20260829/gcc/ada/ChangeLog	Sat Aug 29 22:32:05 2026
***************
*** 1,3 ****
--- 1,19 ----
+ 2026-08-26  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/127026
+ 	* exp_aggr.adb (Must_Slide): Check for the unconstrained case only
+ 	after all the negative tests.
+ 
+ 2026-08-24  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	PR ada/127026
+ 	* exp_aggr.adb (Must_Slide): Reorder parameters, rename Obj_Type to
+ 	Ob_Typ and add Assign boolean parameter.  Return Assign's value in
+ 	the case where Obj_Typ is unconstrained.
+ 	(Build_Array_Aggr_Code): Adjust call to Must_Slide.
+ 	(In_Place_Assign_OK): Likewise.
+ 	(Expand_Array_Aggregate): Likewise.
+ 
  2026-08-19  Eric Botcazou  <ebotcazou@adacore.com>
  
  	PR ada/126928
diff -Nrcpad gcc-16-20260822/gcc/ada/exp_aggr.adb gcc-16-20260829/gcc/ada/exp_aggr.adb
*** gcc-16-20260822/gcc/ada/exp_aggr.adb	Sat Aug 22 22:32:06 2026
--- gcc-16-20260829/gcc/ada/exp_aggr.adb	Sat Aug 29 22:32:05 2026
*************** package body Exp_Aggr is
*** 138,156 ****
     --  constants that are done in place.
  
     function Must_Slide
!      (Aggr     : Node_Id;
!       Obj_Type : Entity_Id;
!       Typ      : Entity_Id) return Boolean;
     --  A static array aggregate in an object declaration can in most cases be
     --  expanded in place. The one exception is when the aggregate is given
     --  with component associations that specify different bounds from those of
     --  the type definition in the object declaration. In this pathological
     --  case the aggregate must slide, and we must introduce an intermediate
!    --  temporary to hold it.
!    --
!    --  The same holds in an assignment to multi-dimensional arrays, when
!    --  components may be given with bounds that differ from those of the
!    --  component type.
  
     function Number_Of_Choices (N : Node_Id) return Nat;
     --  Returns the number of discrete choices (not including the others choice
--- 138,159 ----
     --  constants that are done in place.
  
     function Must_Slide
!      (Aggr    : Node_Id;
!       Typ     : Entity_Id;
!       Obj_Typ : Entity_Id;
!       Assign  : Boolean) return Boolean;
!    --  Return whether an array aggregate Aggr whose subtype is Typ must slide
!    --  when assigned to an object whose (nominal) subtype is Obj_Typ. Assign
!    --  is True when the context is an assignment statement and False when it
!    --  is an object declaration or an allocator.
! 
     --  A static array aggregate in an object declaration can in most cases be
     --  expanded in place. The one exception is when the aggregate is given
     --  with component associations that specify different bounds from those of
     --  the type definition in the object declaration. In this pathological
     --  case the aggregate must slide, and we must introduce an intermediate
!    --  temporary to hold it. The same holds in an assignment, when components
!    --  may be given with bounds that differ from those of the target.
  
     function Number_Of_Choices (N : Node_Id) return Nat;
     --  Returns the number of discrete choices (not including the others choice
*************** package body Exp_Aggr is
*** 1443,1449 ****
                 if Nkind (Parent (N)) = N_Assignment_Statement
                   and then Is_Array_Type (Comp_Typ)
                   and then Present (Component_Associations (Expr_Q))
!                  and then Must_Slide (N, Comp_Typ, Etype (Expr_Q))
                 then
                    Set_Expansion_Delayed (Expr_Q, False);
                    Set_Analyzed (Expr_Q, False);
--- 1446,1453 ----
                 if Nkind (Parent (N)) = N_Assignment_Statement
                   and then Is_Array_Type (Comp_Typ)
                   and then Present (Component_Associations (Expr_Q))
!                  and then
!                    Must_Slide (N, Etype (Expr_Q), Comp_Typ, Assign => True)
                 then
                    Set_Expansion_Delayed (Expr_Q, False);
                    Set_Analyzed (Expr_Q, False);
*************** package body Exp_Aggr is
*** 4245,4251 ****
        --  statically equal to those of the target.
  
        if Is_Array
!         and then Must_Slide (N, Etype (Name (Parent_Node)), Etype (N))
        then
           return False;
        end if;
--- 4249,4256 ----
        --  statically equal to those of the target.
  
        if Is_Array
!         and then
!           Must_Slide (N, Etype (N), Etype (Name (Parent_Node)), Assign => True)
        then
           return False;
        end if;
*************** package body Exp_Aggr is
*** 6270,6277 ****
                         or else Needs_Finalization (Typ)
                         or else not Must_Slide
                                       (N,
                                        Designated_Type (Etype (Parent_Node)),
!                                       Typ)))
  
           --  Object declaration (see Convert_Aggr_In_Object_Decl). Sliding
           --  cannot be done in place for the time being.
--- 6275,6283 ----
                         or else Needs_Finalization (Typ)
                         or else not Must_Slide
                                       (N,
+                                       Typ,
                                        Designated_Type (Etype (Parent_Node)),
!                                       Assign => False)))
  
           --  Object declaration (see Convert_Aggr_In_Object_Decl). Sliding
           --  cannot be done in place for the time being.
*************** package body Exp_Aggr is
*** 6285,6293 ****
                                   (Defining_Identifier (Parent_Node))
                         or else not Must_Slide
                                       (N,
                                        Etype
                                          (Defining_Identifier (Parent_Node)),
!                                       Typ)))
  
           --  Safe assignment (see Convert_Aggr_In_Assignment). So far only the
           --  assignments in init procs are taken into account, as well those
--- 6291,6300 ----
                                   (Defining_Identifier (Parent_Node))
                         or else not Must_Slide
                                       (N,
+                                       Typ,
                                        Etype
                                          (Defining_Identifier (Parent_Node)),
!                                       Assign => False)))
  
           --  Safe assignment (see Convert_Aggr_In_Assignment). So far only the
           --  assignments in init procs are taken into account, as well those
*************** package body Exp_Aggr is
*** 9604,9637 ****
     ----------------
  
     function Must_Slide
!      (Aggr     : Node_Id;
!       Obj_Type : Entity_Id;
!       Typ      : Entity_Id) return Boolean
     is
     begin
!       --  No sliding if the type of the object is not established yet, if it is
!       --  an unconstrained type whose actual subtype comes from the aggregate,
!       --  or if the two types are identical. If the aggregate contains only
!       --  an Others_Clause it gets its type from the context and no sliding
!       --  is involved either.
! 
!       if not Is_Array_Type (Obj_Type) then
!          return False;
  
!       elsif not Is_Constrained (Obj_Type) then
           return False;
  
!       elsif Typ = Obj_Type then
           return False;
  
        elsif Is_Others_Aggregate (Aggr) then
           return False;
  
        --  Check if sliding is required
  
        else
           declare
!             Obj_Index  : Node_Id := First_Index (Obj_Type);
              Obj_Bounds : Range_Nodes;
              Typ_Index  : Node_Id := First_Index (Typ);
              Typ_Bounds : Range_Nodes;
--- 9611,9645 ----
     ----------------
  
     function Must_Slide
!      (Aggr    : Node_Id;
!       Typ     : Entity_Id;
!       Obj_Typ : Entity_Id;
!       Assign  : Boolean) return Boolean
     is
     begin
!       --  No sliding if the type of the object is not established yet, or if
!       --  the two types are identical. And if the aggregate contains only an
!       --  Others_Clause, it gets its type from the context and no sliding is
!       --  involved either. When the type of the object is unconstrained, no
!       --  sliding either if its actual subtype comes from the aggregate.
  
!       if not Is_Array_Type (Obj_Typ) then
           return False;
  
!       elsif Typ = Obj_Typ then
           return False;
  
        elsif Is_Others_Aggregate (Aggr) then
           return False;
  
+       elsif not Is_Constrained (Obj_Typ) then
+          return Assign;
+ 
        --  Check if sliding is required
  
        else
           declare
!             Obj_Index  : Node_Id := First_Index (Obj_Typ);
              Obj_Bounds : Range_Nodes;
              Typ_Index  : Node_Id := First_Index (Typ);
              Typ_Bounds : Range_Nodes;
diff -Nrcpad gcc-16-20260822/gcc/common/config/i386/cpuinfo.h gcc-16-20260829/gcc/common/config/i386/cpuinfo.h
*** gcc-16-20260822/gcc/common/config/i386/cpuinfo.h	Sat Aug 22 22:32:07 2026
--- gcc-16-20260829/gcc/common/config/i386/cpuinfo.h	Sat Aug 29 22:32:06 2026
*************** get_available_features (struct __process
*** 1112,1127 ****
  	}
      }
  
-   /* Get Advanced Features at level 0x21 (eax = 0x21).  */
-   if (max_cpuid_level >= 0x21)
-     {
-       __cpuid (0x21, eax, ebx, ecx, edx);
-       if (eax & bit_AVX512BMM)
- 	{
- 	  set_feature (FEATURE_AVX512BMM);
- 	}
-     }
- 
    /* Get Advanced Features at level 0x24 (eax = 0x24, ecx = 0).  */
    if (avx10_set && max_cpuid_level >= 0x24)
      {
--- 1112,1117 ----
*************** get_available_features (struct __process
*** 1196,1204 ****
      {
        __cpuid (0x80000021, eax, ebx, ecx, edx);
        if (eax & bit_AMD_PREFETCHI)
! 	{
! 	  set_feature (FEATURE_PREFETCHI);
! 	}
      }
  
  #undef set_feature
--- 1186,1194 ----
      {
        __cpuid (0x80000021, eax, ebx, ecx, edx);
        if (eax & bit_AMD_PREFETCHI)
! 	set_feature (FEATURE_PREFETCHI);
!       if (eax & bit_AVX512BMM)
! 	set_feature (FEATURE_AVX512BMM);
      }
  
  #undef set_feature
diff -Nrcpad gcc-16-20260822/gcc/config/aarch64/aarch64-sys-regs.def gcc-16-20260829/gcc/config/aarch64/aarch64-sys-regs.def
*** gcc-16-20260822/gcc/config/aarch64/aarch64-sys-regs.def	Sat Aug 22 22:32:07 2026
--- gcc-16-20260829/gcc/config/aarch64/aarch64-sys-regs.def	Sat Aug 29 22:32:06 2026
***************
*** 1357,1362 ****
--- 1357,1370 ----
    SYSREG ("tindex_el2",		CPENC (3,4,4,0,3),	0,		AARCH64_FEATURE (POE2))
    SYSREG ("tindex_el3",		CPENC (3,6,4,0,3),	0,		AARCH64_FEATURE (POE2))
    SYSREG ("tlbididr_el1",	CPENC (3,0,10,4,6),	F_REG_READ,	AARCH64_FEATURE (TLBID))
+   SYSREG ("tpcr0_el0",		CPENC (3,3,2,2,4),	0,		AARCH64_NO_FEATURES)
+   SYSREG ("tpcr0_el1",		CPENC (3,0,2,2,4),	0,		AARCH64_NO_FEATURES)
+   SYSREG ("tpcr0_el12",		CPENC (3,5,2,2,4),	0,		AARCH64_NO_FEATURES)
+   SYSREG ("tpcr0_el2",		CPENC (3,4,2,2,4),	0,		AARCH64_NO_FEATURES)
+   SYSREG ("tpcr1_el0",		CPENC (3,3,2,2,5),	0,		AARCH64_NO_FEATURES)
+   SYSREG ("tpcr1_el1",		CPENC (3,0,2,2,5),	0,		AARCH64_NO_FEATURES)
+   SYSREG ("tpcr1_el12",		CPENC (3,5,2,2,5),	0,		AARCH64_NO_FEATURES)
+   SYSREG ("tpcr1_el2",		CPENC (3,4,2,2,5),	0,		AARCH64_NO_FEATURES)
    SYSREG ("tpidr2_el0",		CPENC (3,3,13,0,5),	0,		AARCH64_FEATURE (SME))
    SYSREG ("tpidr3_el0",		CPENC (3,3,13,0,0),     0,		AARCH64_FEATURE (POE2))
    SYSREG ("tpidr3_el1",		CPENC (3,0,13,0,0),	0,		AARCH64_FEATURE (POE2))
***************
*** 1368,1389 ****
    SYSREG ("tpidr_el2",		CPENC (3,4,13,0,2),	0,		AARCH64_NO_FEATURES)
    SYSREG ("tpidr_el3",		CPENC (3,6,13,0,2),	0,		AARCH64_NO_FEATURES)
    SYSREG ("tpidrro_el0",	CPENC (3,3,13,0,3),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax0_el0",		CPENC (3,3,2,2,5),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax0_el1",		CPENC (3,0,2,2,5),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax0_el12",	CPENC (3,5,2,2,5),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax0_el2",		CPENC (3,4,2,2,5),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax1_el0",		CPENC (3,3,2,2,7),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax1_el1",		CPENC (3,0,2,2,7),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax1_el12",	CPENC (3,5,2,2,7),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmax1_el2",		CPENC (3,4,2,2,7),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin0_el0",		CPENC (3,3,2,2,4),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin0_el1",		CPENC (3,0,2,2,4),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin0_el12",	CPENC (3,5,2,2,4),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin0_el2",		CPENC (3,4,2,2,4),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin1_el0",		CPENC (3,3,2,2,6),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin1_el1",		CPENC (3,0,2,2,6),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin1_el12",	CPENC (3,5,2,2,6),	0,		AARCH64_NO_FEATURES)
-   SYSREG ("tpmin1_el2",		CPENC (3,4,2,2,6),	0,		AARCH64_NO_FEATURES)
    SYSREG ("trbbaser_el1",	CPENC (3,0,9,11,2),	0,		AARCH64_FEATURE (V9A)) /* TRBE */
    SYSREG ("trbidr_el1",		CPENC (3,0,9,11,7),	F_REG_READ,	AARCH64_FEATURE (V9A)) /* TRBE */
    SYSREG ("trblimitr_el1",	CPENC (3,0,9,11,0),	0,		AARCH64_FEATURE (V9A)) /* TRBE */
--- 1376,1381 ----
diff -Nrcpad gcc-16-20260822/gcc/config/avr/avr-passes.cc gcc-16-20260829/gcc/config/avr/avr-passes.cc
*** gcc-16-20260822/gcc/config/avr/avr-passes.cc	Sat Aug 22 22:32:07 2026
--- gcc-16-20260829/gcc/config/avr/avr-passes.cc	Sat Aug 29 22:32:06 2026
***************
*** 28,33 ****
--- 28,34 ----
  #include "backend.h"
  #include "target.h"
  #include "rtl.h"
+ #include "rtl-iter.h"
  #include "tree.h"
  #include "diagnostic-core.h"
  #include "cfghooks.h"
*************** struct insninfo_t
*** 1053,1058 ****
--- 1054,1081 ----
      else
        gcc_unreachable ();
    }
+ 
+   gprmask_t scratch_mask () const
+   {
+     gprmask_t mask = m_scratch
+       ? regmask (m_scratch, 1)
+       : 0;
+ 
+     if (m_insn)
+       {
+ 	subrtx_iterator::array_type array;
+ 	FOR_EACH_SUBRTX (iter, array, PATTERN (m_insn), NONCONST)
+ 	  {
+ 	    rtx scratch_reg;
+ 	    if (GET_CODE (*iter) == CLOBBER
+ 		&& REG_P (scratch_reg = XEXP (*iter, 0))
+ 		&& END_REGNO (scratch_reg) <= REG_32)
+ 	      mask |= regmask (scratch_reg);
+ 	  }
+       }
+ 
+     return mask;
+   }
  }; // insninfo_t
  
  
*************** optimize_data_t::emit_sequence (basic_bl
*** 1186,1191 ****
--- 1209,1215 ----
  	  avr_dump ("INCOMPLETE APPLICATION:\n");
  	  m2.dump ("regs old route=%s\n\n");
  	  n2.dump ("regs new route=%s\n\n");
+ 	  avr_dump ("ignore_mask = %08x\n\n", (unsigned) ignore_mask);
  	  avr_dump ("The new insns are:\n%L", insns);
  
  	  fatal_insn ("incomplete application of insn", insns);
*************** optimize_data_t::try_split_ldi (bbinfo_t
*** 2714,2721 ****
  
        n_new_insns = bbinfo_t::fpd->solution.emit_insns (curr.ii, curr.regs);
  
!       if (curr.ii.m_scratch)
! 	ignore_mask = regmask (curr.ii.m_scratch, 1);
      }
  
    return found;
--- 2738,2744 ----
  
        n_new_insns = bbinfo_t::fpd->solution.emit_insns (curr.ii, curr.regs);
  
!       ignore_mask = curr.ii.scratch_mask ();
      }
  
    return found;
*************** optimize_data_t::try_split_any (bbinfo_t
*** 3056,3063 ****
  	return fail ("too expensive");
      }
  
!   if (ii.m_scratch)
!     ignore_mask = regmask (ii.m_scratch, 1);
  
    return true;
  }
--- 3079,3085 ----
  	return fail ("too expensive");
      }
  
!   ignore_mask = ii.scratch_mask ();
  
    return true;
  }
diff -Nrcpad gcc-16-20260822/gcc/config/avr/avr.h gcc-16-20260829/gcc/config/avr/avr.h
*** gcc-16-20260822/gcc/config/avr/avr.h	Sat Aug 22 22:32:07 2026
--- gcc-16-20260829/gcc/config/avr/avr.h	Sat Aug 29 22:32:06 2026
*************** enum reg_class {
*** 321,330 ****
  
  #define RETURN_ADDR_RTX(count, tem) avr_return_addr_rtx (count, tem)
  
- /* Don't use Push rounding. expr.cc: emit_single_push_insn is broken
-    for POST_DEC targets (PR27386).  */
- /*#define PUSH_ROUNDING(NPUSHED) (NPUSHED)*/
- 
  typedef struct avr_args
  {
    /* # Registers available for passing */
--- 321,326 ----
*************** struct GTY(()) machine_function
*** 603,609 ****
  };
  
  /* AVR does not round pushes, but the existence of this macro is
!    required in order for pushes to be generated.  */
  #define PUSH_ROUNDING(X)	(X)
  
  /* Define prototype here to avoid build warning.  Some files using
--- 599,609 ----
  };
  
  /* AVR does not round pushes, but the existence of this macro is
!    required in order for pushes to be generated.
!    This macro was removed for PR27386 and then later re-added when
!    push insns were introduced.  Push insns can work around broken
!    argument setup in expr.cc that doesn't work properly for
!    STACK_GROWS_DOWNWARDS + POST_DEC push, see PR127098.  */
  #define PUSH_ROUNDING(X)	(X)
  
  /* Define prototype here to avoid build warning.  Some files using
diff -Nrcpad gcc-16-20260822/gcc/config/avr/avr.md gcc-16-20260829/gcc/config/avr/avr.md
*** gcc-16-20260822/gcc/config/avr/avr.md	Sat Aug 22 22:32:07 2026
--- gcc-16-20260829/gcc/config/avr/avr.md	Sat Aug 29 22:32:06 2026
***************
*** 478,484 ****
     HI CHI HA UHA HQ UHQ
     SI CSI SA USA SQ USQ
     DI CDI DA UDA DQ UDQ
!    TA UTA
     SF DF SC DC
     PSI])
  
--- 478,484 ----
     HI CHI HA UHA HQ UHQ
     SI CSI SA USA SQ USQ
     DI CDI DA UDA DQ UDQ
!    TA UTA TI
     SF DF SC DC
     PSI])
  
diff -Nrcpad gcc-16-20260822/gcc/config/i386/cpuid.h gcc-16-20260829/gcc/config/i386/cpuid.h
*** gcc-16-20260822/gcc/config/i386/cpuid.h	Sat Aug 22 22:32:07 2026
--- gcc-16-20260829/gcc/config/i386/cpuid.h	Sat Aug 29 22:32:06 2026
***************
*** 75,80 ****
--- 75,81 ----
  /* Extended Features (%eax == 0x80000021) */
  /* %eax */
  #define bit_AMD_PREFETCHI (1 << 20)
+ #define bit_AVX512BMM (1 << 23)
  
  /* Extended Features Leaf (%eax == 7, %ecx == 0) */
  /* %ebx */
***************
*** 167,175 ****
  #define bit_AESKLE	( 1<<0 )
  #define bit_WIDEKL	( 1<<2 )
  
- /* Sub leaf (%eax == 0x21) */
- #define bit_AVX512BMM	( 1<<23 )
- 
  /* AMX sub leaf (%eax == 0x1e, %ecx == 1) */
  /* %eax */
  #define bit_AMX_FP8	(1 << 4)
--- 168,173 ----
diff -Nrcpad gcc-16-20260822/gcc/config/riscv/autovec.md gcc-16-20260829/gcc/config/riscv/autovec.md
*** gcc-16-20260822/gcc/config/riscv/autovec.md	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/riscv/autovec.md	Sat Aug 29 22:32:06 2026
***************
*** 1383,1389 ****
  
        /* Here we set VL = offset + 1.  */
        rtx length = gen_reg_rtx (Pmode);
!       operands[2] = gen_lowpart (Pmode, operands[2]);
        if (CONST_INT_P (operands[2]))
  	  emit_move_insn (length, GEN_INT (INTVAL (operands[2]) + 1));
        else
--- 1383,1389 ----
  
        /* Here we set VL = offset + 1.  */
        rtx length = gen_reg_rtx (Pmode);
!       operands[2] = convert_to_mode (Pmode, operands[2], true);
        if (CONST_INT_P (operands[2]))
  	  emit_move_insn (length, GEN_INT (INTVAL (operands[2]) + 1));
        else
***************
*** 1439,1445 ****
  
      /* Emit the slide down to index 0 in a new vector.  */
      tmp = gen_reg_rtx (<MODE>mode);
!     operands[2] = gen_lowpart (Pmode, operands[2]);
      rtx ops[] = {tmp, operands[1], operands[2]};
      riscv_vector::emit_vlmax_insn
        (code_for_pred_slide (UNSPEC_VSLIDEDOWN, <MODE>mode),
--- 1439,1445 ----
  
      /* Emit the slide down to index 0 in a new vector.  */
      tmp = gen_reg_rtx (<MODE>mode);
!     operands[2] = convert_to_mode (Pmode, operands[2], true);
      rtx ops[] = {tmp, operands[1], operands[2]};
      riscv_vector::emit_vlmax_insn
        (code_for_pred_slide (UNSPEC_VSLIDEDOWN, <MODE>mode),
diff -Nrcpad gcc-16-20260822/gcc/config/riscv/riscv-cores.def gcc-16-20260829/gcc/config/riscv/riscv-cores.def
*** gcc-16-20260822/gcc/config/riscv/riscv-cores.def	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/riscv/riscv-cores.def	Sat Aug 29 22:32:06 2026
*************** RISCV_TUNE("sifive-7-series", sifive_7,
*** 41,46 ****
--- 41,47 ----
  RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info)
  RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info)
  RISCV_TUNE("tt-ascalon-x", tt_ascalon_d8, tt_ascalon_d8_tune_info)
+ RISCV_TUNE("tt-ascalon-xg", tt_ascalon_xg, tt_ascalon_d8_tune_info)
  RISCV_TUNE("tt-ascalon-d8", tt_ascalon_d8, tt_ascalon_d8_tune_info)
  RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
  RISCV_TUNE("xt-c908", generic, generic_ooo_tune_info)
*************** RISCV_CORE("tt-ascalon-d8",   "rva23s64_
*** 158,163 ****
--- 159,169 ----
  			      "smstateen_ssaia_ssstrict_svadu",
  			      "tt-ascalon-d8")
  
+ RISCV_CORE("tt-ascalon-xg",   "rva23s64_zfbfmin_zfh_zkr_zvbc_zvfbfmin_zvfbfwma_"
+ 			      "zvfh_zvl256b_smaia_smmpm_smnpm_smrnmi_smstateen_"
+ 			      "ssaia_ssstrict_svadu",
+ 			      "tt-ascalon-xg")
+ 
  RISCV_CORE("xiangshan-nanhu",      "rv64imafdc_zba_zbb_zbc_zbs_"
  			      "zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_"
  			      "svinval_zicbom_zicboz",
diff -Nrcpad gcc-16-20260822/gcc/config/riscv/riscv-opts.h gcc-16-20260829/gcc/config/riscv/riscv-opts.h
*** gcc-16-20260822/gcc/config/riscv/riscv-opts.h	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/riscv/riscv-opts.h	Sat Aug 29 22:32:06 2026
*************** enum riscv_microarchitecture_type {
*** 61,66 ****
--- 61,67 ----
    generic_ooo,
    mips_p8700,
    tt_ascalon_d8,
+   tt_ascalon_xg,
    andes_25_series,
    andes_23_series,
    andes_45_series,
diff -Nrcpad gcc-16-20260822/gcc/config/riscv/riscv.md gcc-16-20260829/gcc/config/riscv/riscv.md
*** gcc-16-20260822/gcc/config/riscv/riscv.md	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/riscv/riscv.md	Sat Aug 29 22:32:06 2026
***************
*** 674,680 ****
  ;; Keep this in sync with enum riscv_microarchitecture.
  (define_attr "tune"
    "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,
!    tt_ascalon_d8,andes_25_series,andes_23_series,andes_45_series,spacemit_x60"
    (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
  
  ;; Describe a user's asm statement.
--- 674,681 ----
  ;; Keep this in sync with enum riscv_microarchitecture.
  (define_attr "tune"
    "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700,
!    tt_ascalon_d8,tt_ascalon_xg,andes_25_series,andes_23_series,andes_45_series,
!    spacemit_x60"
    (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
  
  ;; Describe a user's asm statement.
diff -Nrcpad gcc-16-20260822/gcc/config/riscv/tt-ascalon-d8.md gcc-16-20260829/gcc/config/riscv/tt-ascalon-d8.md
*** gcc-16-20260822/gcc/config/riscv/tt-ascalon-d8.md	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/riscv/tt-ascalon-d8.md	Sat Aug 29 22:32:06 2026
***************
*** 27,32 ****
--- 27,33 ----
  (define_cpu_unit "asc-fxu0,asc-fxu1,asc-fxu2,asc-fxu3,asc-fxu4,asc-fxu5" "tt_ascalon_d8")
  (define_cpu_unit "asc-fpu0,asc-fpu1" "tt_ascalon_d8")
  (define_cpu_unit "asc-vec0,asc-vec1" "tt_ascalon_d8")
+ (define_cpu_unit "asc-xg-fp64-vec0,asc-xg-fp64-vec1" "tt_ascalon_d8")
  
  ;; Shortcuts
  (define_reservation "tt_ascalon_d8_decode" "asc-decode0|asc-decode1|asc-decode2|asc-decode3|asc-decode4|asc-decode5|asc-decode6|asc-decode7")
***************
*** 41,56 ****
  (define_reservation "tt_ascalon_d8_vec0" "asc-vec0")
  (define_reservation "tt_ascalon_d8_vec1" "asc-vec1")
  (define_reservation "tt_ascalon_d8_vec" "asc-vec0|asc-vec1")
  
  ;; Integer/float load/store
  (define_insn_reservation "tt_ascalon_d8_int_load" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "load,store,fpload,fpstore"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  ;; Generic integer instructions.
  (define_insn_reservation "tt_ascalon_d8_alu" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
  			move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
  			condmove,mvpair,zicond"))
--- 42,58 ----
  (define_reservation "tt_ascalon_d8_vec0" "asc-vec0")
  (define_reservation "tt_ascalon_d8_vec1" "asc-vec1")
  (define_reservation "tt_ascalon_d8_vec" "asc-vec0|asc-vec1")
+ (define_reservation "tt_ascalon_xg_fp64_vec" "asc-xg-fp64-vec0*4 | asc-xg-fp64-vec1*4")
  
  ;; Integer/float load/store
  (define_insn_reservation "tt_ascalon_d8_int_load" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "load,store,fpload,fpstore"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  ;; Generic integer instructions.
  (define_insn_reservation "tt_ascalon_d8_alu" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,\
  			move,bitmanip,rotate,min,max,minu,maxu,clz,ctz,atomic,\
  			condmove,mvpair,zicond"))
***************
*** 58,70 ****
  
  ;; Short forward branch
  (define_insn_reservation "tt_ascalon_d8_sfb" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "sfb_alu"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_br")
  
  ;; Branch instructions
  (define_insn_reservation "tt_ascalon_d8_branch" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_br")
  
--- 60,72 ----
  
  ;; Short forward branch
  (define_insn_reservation "tt_ascalon_d8_sfb" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "sfb_alu"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_br")
  
  ;; Branch instructions
  (define_insn_reservation "tt_ascalon_d8_branch" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "branch,jump,call,jalr,ret,trap"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_br")
  
***************
*** 72,94 ****
  ;; INT -> FP moves are executed by the FXU and FP -> INT moves
  ;; are executed by the FPU, but we can't model that at the moment.
  (define_insn_reservation "tt_ascalon_d8_float_move" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "fmove"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  (define_insn_reservation "tt_ascalon_d8_fcvt" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  (define_insn_reservation "tt_ascalon_d8_fcmp" 2
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "fcmp"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Integer multiplication.
  (define_insn_reservation "tt_ascalon_d8_imul" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "imul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_mul")
  
--- 74,96 ----
  ;; INT -> FP moves are executed by the FXU and FP -> INT moves
  ;; are executed by the FPU, but we can't model that at the moment.
  (define_insn_reservation "tt_ascalon_d8_float_move" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "fmove"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  (define_insn_reservation "tt_ascalon_d8_fcvt" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "fcvt,fcvt_i2f,fcvt_f2i"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  (define_insn_reservation "tt_ascalon_d8_fcmp" 2
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "fcmp"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Integer multiplication.
  (define_insn_reservation "tt_ascalon_d8_imul" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "imul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_mul")
  
***************
*** 97,212 ****
  ;; non-pipelined instructions. Division is variable cycles so pick a value
  ;; in the middle.
  (define_insn_reservation "tt_ascalon_d8_idiv" 15
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "idiv"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_div,tt_ascalon_d8_div*3")
  
  ;; Float addition.
  (define_insn_reservation "tt_ascalon_d8_fadd" 2
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "fadd"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Float multiplication.
  (define_insn_reservation "tt_ascalon_d8_mul" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "fmul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Float FMA.
  (define_insn_reservation "tt_ascalon_d8_float_fma" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "fmadd"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Float division.
  (define_insn_reservation "tt_ascalon_d8_float_div_half" 6
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (and (eq_attr "type" "fdiv,fsqrt")
  	    (eq_attr "mode" "HF")))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_float_div_single" 9
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (and (eq_attr "type" "fdiv,fsqrt")
  	    (eq_attr "mode" "SF")))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_float_div_double" 16
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (and (eq_attr "type" "fdiv,fsqrt")
  	    (eq_attr "mode" "DF")))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
  
  ;; Popcount and clmul.
  (define_insn_reservation "tt_ascalon_d8_popcount" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "cpop,clmul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_alu")
  
  ;; Vector loads and stores
  (define_insn_reservation "tt_ascalon_d8_vec_load" 5
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vlde,vldm,vldff,vldr"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_store" 5
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vste,vstm,vstr"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_load_strided" 16
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vlds"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_store_strided" 16
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vsts"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_load_indexed" 16
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vldux,vldox"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_store_indexed" 16
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vstux,vstox"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  ;; Vector segment loads/stores.
  (define_insn_reservation "tt_ascalon_d8_vec_loadstore_seg" 11
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
  			vssegte,vssegts,vssegtux,vssegtox"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Regular vector operations and integer comparisons.
  (define_insn_reservation "tt_ascalon_d8_vec_alu_1" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vector,vialu,vicalu,viminmax,vimov,vmov,vfmov,\
  			vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_alu_2" 2
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vshift,vsshift,vsalu,vaalu,vext"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_alu_3" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "viwalu,vnshift,vwsll,vicmp"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_alu_4" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vnclip"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector float comparison, conversion etc.
  (define_insn_reservation "tt_ascalon_d8_vec_fcmp" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
  			vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
  			vfncvtftoi,vfncvtftof,vfncvtbf16,vfwcvtbf16"))
--- 99,217 ----
  ;; non-pipelined instructions. Division is variable cycles so pick a value
  ;; in the middle.
  (define_insn_reservation "tt_ascalon_d8_idiv" 15
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "idiv"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_div,tt_ascalon_d8_div*3")
  
  ;; Float addition.
  (define_insn_reservation "tt_ascalon_d8_fadd" 2
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "fadd"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Float multiplication.
  (define_insn_reservation "tt_ascalon_d8_mul" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "fmul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Float FMA.
  (define_insn_reservation "tt_ascalon_d8_float_fma" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "fmadd"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_fp")
  
  ;; Float division.
  (define_insn_reservation "tt_ascalon_d8_float_div_half" 6
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (and (eq_attr "type" "fdiv,fsqrt")
  	    (eq_attr "mode" "HF")))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_float_div_single" 9
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (and (eq_attr "type" "fdiv,fsqrt")
  	    (eq_attr "mode" "SF")))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_float_div_double" 16
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (and (eq_attr "type" "fdiv,fsqrt")
  	    (eq_attr "mode" "DF")))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_fp0*3 | tt_ascalon_d8_fp1*3)")
  
  ;; Popcount and clmul.
  (define_insn_reservation "tt_ascalon_d8_popcount" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "cpop,clmul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_alu")
  
  ;; Vector loads and stores
  (define_insn_reservation "tt_ascalon_d8_vec_load" 5
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vlde,vldm,vldff,vldr"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_store" 5
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vste,vstm,vstr"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_load_strided" 16
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vlds"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_store_strided" 16
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vsts"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_load_indexed" 16
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vldux,vldox"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  (define_insn_reservation "tt_ascalon_d8_vec_store_indexed" 16
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vstux,vstox"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_ls")
  
  ;; Vector segment loads/stores.
  (define_insn_reservation "tt_ascalon_d8_vec_loadstore_seg" 11
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
  			vssegte,vssegts,vssegtux,vssegtox"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Regular vector operations and integer comparisons.
  (define_insn_reservation "tt_ascalon_d8_vec_alu_1" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vector,vialu,vicalu,viminmax,vimov,vmov,vfmov,\
  			vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_alu_2" 2
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vshift,vsshift,vsalu,vaalu,vext"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_alu_3" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "viwalu,vnshift,vwsll,vicmp"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_alu_4" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vnclip"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector float comparison, conversion etc.
  (define_insn_reservation "tt_ascalon_d8_vec_fcmp" 3
!   (and (ior (eq_attr "tune" "tt_ascalon_d8")
! 	    (and (eq_attr "tune" "tt_ascalon_xg")
! 		 (not (and (eq_attr "type" "vfwcvtitof,vfwcvtftof")
! 			   (eq_attr "sew" "32")))))
         (eq_attr "type" "vfrecp,vfminmax,vfcmp,vfsgnj,vfclass,vfcvtitof,\
  			vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
  			vfncvtftoi,vfncvtftof,vfncvtbf16,vfwcvtbf16"))
***************
*** 214,274 ****
  
  ;; Vector integer multiplication.
  (define_insn_reservation "tt_ascalon_d8_vec_imul" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
  			vghsh,vgmul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector float addition.
  (define_insn_reservation "tt_ascalon_d8_vec_fadd" 2
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vfalu,vfwalu"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector float multiplication and FMA.
  (define_insn_reservation "tt_ascalon_d8_vec_fmul" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector population count.
  (define_insn_reservation "tt_ascalon_d8_vec_pop" 2
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vcpop"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector crypto, AES.
  (define_insn_reservation "tt_ascalon_d8_vec_crypto_aes" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "crypto,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector SHA.
  (define_insn_reservation "tt_ascalon_d8_vec_crypto_sha" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector permute.
  (define_insn_reservation "tt_ascalon_d8_vec_perm_1" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vimerge,vfmerge"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_perm_3" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vislide1up,vislide1down,vfslide1up,vfslide1down,\
  			vgather,vcompress"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_perm_4" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vslideup,vslidedown"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector reduction.
  (define_insn_reservation "tt_ascalon_d8_vec_reduction" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vired,viwred,vfredu,vfwredu"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
--- 219,299 ----
  
  ;; Vector integer multiplication.
  (define_insn_reservation "tt_ascalon_d8_vec_imul" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vimul,viwmul,vimuladd,viwmuladd,vsmul,vclmul,vclmulh,\
  			vghsh,vgmul"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector float addition.
  (define_insn_reservation "tt_ascalon_d8_vec_fadd" 2
!   (and (ior (eq_attr "tune" "tt_ascalon_d8")
! 	    (and (eq_attr "tune" "tt_ascalon_xg")
! 		 (not (eq_attr "sew" "64"))
! 		 (not (and (eq_attr "type" "vfwalu")
! 			   (eq_attr "sew" "32")))))
         (eq_attr "type" "vfalu,vfwalu"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector float multiplication and FMA.
  (define_insn_reservation "tt_ascalon_d8_vec_fmul" 4
!   (and (ior (eq_attr "tune" "tt_ascalon_d8")
! 	    (and (eq_attr "tune" "tt_ascalon_xg")
! 		 (not (eq_attr "sew" "64"))
! 		 (not (and (eq_attr "type" "vfwmul,vfwmuladd")
! 			   (eq_attr "sew" "32")))))
         (eq_attr "type" "vfmul,vfwmul,vfmuladd,vfwmuladd,vfwmaccbf16"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
+ ;; The global version of Ascalon X (tt-ascalon-xg) has reduced FP64 throughput
+ ;; compared to Ascalon X in order to meet export restrictions.  Implement the
+ ;; reduced throughput via an extra vector pipeline stage used only by the
+ ;; affected instructions.  All other vector instructions are unaffected.
+ (define_insn_reservation "tt_ascalon_xg_fp64_vec_insns" 9
+   (and (eq_attr "tune" "tt_ascalon_xg")
+        (ior (and (eq_attr "type" "vfalu,vfmul,vfmuladd")
+ 		 (eq_attr "sew" "64"))
+ 	    (and (eq_attr "type" "vfwalu,vfwmul,vfwmuladd,vfwcvtftof,vfwcvtitof")
+ 		 (eq_attr "sew" "32"))))
+   "tt_ascalon_d8_decode,tt_ascalon_d8_vec,tt_ascalon_xg_fp64_vec")
+ 
  ;; Vector population count.
  (define_insn_reservation "tt_ascalon_d8_vec_pop" 2
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vcpop"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector crypto, AES.
  (define_insn_reservation "tt_ascalon_d8_vec_crypto_aes" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "crypto,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector SHA.
  (define_insn_reservation "tt_ascalon_d8_vec_crypto_sha" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vsha2ms,vsha2ch,vsha2cl"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector permute.
  (define_insn_reservation "tt_ascalon_d8_vec_perm_1" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vimerge,vfmerge"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_perm_3" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vislide1up,vislide1down,vfslide1up,vfslide1down,\
  			vgather,vcompress"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  (define_insn_reservation "tt_ascalon_d8_vec_perm_4" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vslideup,vslidedown"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector reduction.
  (define_insn_reservation "tt_ascalon_d8_vec_reduction" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vired,viwred,vfredu,vfwredu"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
***************
*** 277,358 ****
  ;; riscv_sched_adjust_cost for larger vectors.
  ;; NOTE: The latency depends on the SEW, we should be checking it
  (define_insn_reservation "tt_ascalon_d8_vec_ordered_reduction" 10
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vfredo,vfwredo"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  ;; Vector integer division
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_byte" 16
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "8"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_half" 16
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "16"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_single" 13
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "32"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_double" 20
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "64"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  ;; Vector float divisions and sqrt
  (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_half" 11
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vfdiv,vfsqrt")
         (eq_attr "sew" "16"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_single" 10
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vfdiv,vfsqrt")
         (eq_attr "sew" "32"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_double" 17
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vfdiv,vfsqrt")
         (eq_attr "sew" "64"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  ;; Vector mask operations.
  (define_insn_reservation "tt_ascalon_d8_vec_mask" 3
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
  			vfmovvf,vfmovfv"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector vsetvl.
  (define_insn_reservation "tt_ascalon_d8_vec_vesetvl" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "vsetvl,vsetvl_pre"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector rounding mode setters, assume pipeline barrier.
  (define_insn_reservation "tt_ascalon_d8_vec_setrm" 20
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "wrvxrm,wrfrm"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec*3")
  
  ;; Vector read vlen/vlenb.
  (define_insn_reservation "tt_ascalon_d8_vec_readlen" 4
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "rdvlenb,rdvl"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector unknown.
  (define_insn_reservation "tt_ascalon_d8_vec_unknown" 1
!   (and (eq_attr "tune" "tt_ascalon_d8")
         (eq_attr "type" "sf_vc,sf_vc_se,sf_vqmacc,sf_vfnrclip,\
  			vsm3me,vsm4r,vsm4k,vsm3c,ghost,\
  			mfc,mtc,rdfrm"))
--- 302,383 ----
  ;; riscv_sched_adjust_cost for larger vectors.
  ;; NOTE: The latency depends on the SEW, we should be checking it
  (define_insn_reservation "tt_ascalon_d8_vec_ordered_reduction" 10
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vfredo,vfwredo"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  ;; Vector integer division
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_byte" 16
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "8"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_half" 16
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "16"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_single" 13
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "32"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_idiv_double" 20
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vidiv")
         (eq_attr "sew" "64"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  ;; Vector float divisions and sqrt
  (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_half" 11
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vfdiv,vfsqrt")
         (eq_attr "sew" "16"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_single" 10
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vfdiv,vfsqrt")
         (eq_attr "sew" "32"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  (define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_double" 17
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vfdiv,vfsqrt")
         (eq_attr "sew" "64"))
    "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
  
  ;; Vector mask operations.
  (define_insn_reservation "tt_ascalon_d8_vec_mask" 3
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,\
  			vfmovvf,vfmovfv"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector vsetvl.
  (define_insn_reservation "tt_ascalon_d8_vec_vesetvl" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "vsetvl,vsetvl_pre"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector rounding mode setters, assume pipeline barrier.
  (define_insn_reservation "tt_ascalon_d8_vec_setrm" 20
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "wrvxrm,wrfrm"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec*3")
  
  ;; Vector read vlen/vlenb.
  (define_insn_reservation "tt_ascalon_d8_vec_readlen" 4
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "rdvlenb,rdvl"))
    "tt_ascalon_d8_decode,tt_ascalon_d8_vec")
  
  ;; Vector unknown.
  (define_insn_reservation "tt_ascalon_d8_vec_unknown" 1
!   (and (eq_attr "tune" "tt_ascalon_d8,tt_ascalon_xg")
         (eq_attr "type" "sf_vc,sf_vc_se,sf_vqmacc,sf_vfnrclip,\
  			vsm3me,vsm4r,vsm4k,vsm3c,ghost,\
  			mfc,mtc,rdfrm"))
diff -Nrcpad gcc-16-20260822/gcc/config/rs6000/linux64.h gcc-16-20260829/gcc/config/rs6000/linux64.h
*** gcc-16-20260822/gcc/config/rs6000/linux64.h	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/rs6000/linux64.h	Sat Aug 29 22:32:06 2026
*************** extern int dot_symbols;
*** 564,570 ****
  
  /* Enable using prefixed PC-relative addressing on POWER10 if the ABI
     supports it.  The ELF v2 ABI only supports PC-relative relocations for
!    the medium code model.  */
  #define PCREL_SUPPORTED_BY_OS	(TARGET_POWER10 && TARGET_PREFIXED	\
  				 && ELFv2_ABI_CHECK			\
! 				 && TARGET_CMODEL == CMODEL_MEDIUM)
--- 564,571 ----
  
  /* Enable using prefixed PC-relative addressing on POWER10 if the ABI
     supports it.  The ELF v2 ABI only supports PC-relative relocations for
!    the medium/large code models.  */
  #define PCREL_SUPPORTED_BY_OS	(TARGET_POWER10 && TARGET_PREFIXED	\
  				 && ELFv2_ABI_CHECK			\
! 				 && (TARGET_CMODEL == CMODEL_MEDIUM	\
! 				     || TARGET_CMODEL == CMODEL_LARGE))
diff -Nrcpad gcc-16-20260822/gcc/config/rs6000/rs6000-cpus.def gcc-16-20260829/gcc/config/rs6000/rs6000-cpus.def
*** gcc-16-20260822/gcc/config/rs6000/rs6000-cpus.def	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/rs6000/rs6000-cpus.def	Sat Aug 29 22:32:06 2026
***************
*** 83,91 ****
  #define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER			\
  			      | OPTION_MASK_POWER11)
  
! /* -mcpu=future flags.  */
  #define FUTURE_MASKS_SERVER	(POWER11_MASKS_SERVER			\
  				 | OPTION_MASK_FUTURE			\
  				 | OPTION_MASK_DMF)
  
  /* Flags that need to be turned off if -mno-vsx.  */
--- 83,98 ----
  #define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER			\
  			      | OPTION_MASK_POWER11)
  
! /* -mcpu=future flags.
! 
!    During the development of the power10 support for GCC, using load/store
!    vector pair instructions for string operations was turned off by default,
!    because there was a use case that had really bad performance.  Assume this
!    will be fixed in potential future machines.  */
! 
  #define FUTURE_MASKS_SERVER	(POWER11_MASKS_SERVER			\
  				 | OPTION_MASK_FUTURE			\
+ 				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
  				 | OPTION_MASK_DMF)
  
  /* Flags that need to be turned off if -mno-vsx.  */
***************
*** 116,121 ****
--- 123,129 ----
  
  /* Mask of all options to set the default isa flags based on -mcpu=<xxx>.  */
  #define POWERPC_MASKS		(OPTION_MASK_ALTIVEC			\
+ 				 | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR	\
  				 | OPTION_MASK_CMPB			\
  				 | OPTION_MASK_CRYPTO			\
  				 | OPTION_MASK_DFP			\
diff -Nrcpad gcc-16-20260822/gcc/config/rs6000/rs6000.cc gcc-16-20260829/gcc/config/rs6000/rs6000.cc
*** gcc-16-20260822/gcc/config/rs6000/rs6000.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/rs6000/rs6000.cc	Sat Aug 29 22:32:06 2026
*************** rs6000_option_override_internal (bool gl
*** 4426,4437 ****
        && (rs6000_isa_flags_explicit & OPTION_MASK_PCREL) == 0)
      rs6000_isa_flags |= OPTION_MASK_PCREL;
  
!   /* -mpcrel requires -mcmodel=medium, but we can't check TARGET_CMODEL until
!       after the subtarget override options are done.  */
!   else if (TARGET_PCREL && TARGET_CMODEL != CMODEL_MEDIUM)
      {
        if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
! 	error ("%qs requires %qs", "-mpcrel", "-mcmodel=medium");
  
        rs6000_isa_flags &= ~OPTION_MASK_PCREL;
      }
--- 4426,4440 ----
        && (rs6000_isa_flags_explicit & OPTION_MASK_PCREL) == 0)
      rs6000_isa_flags |= OPTION_MASK_PCREL;
  
!   /* -mpcrel requires medium or large code models, but we can't check
!       TARGET_CMODEL until after the subtarget override options are done.  */
!   else if (TARGET_PCREL
! 	   && TARGET_CMODEL != CMODEL_MEDIUM
! 	   && TARGET_CMODEL != CMODEL_LARGE)
      {
        if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
! 	error ("%qs requires %qs or %qs", "-mpcrel", "-mcmodel=medium",
! 	       "-mcmodel=large");
  
        rs6000_isa_flags &= ~OPTION_MASK_PCREL;
      }
*************** rs6000_machine_from_flags (void)
*** 5992,5998 ****
  
    /* Disable the flags that should never influence the .machine selection.  */
    flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
! 	     | OPTION_MASK_ALTIVEC);
  
    if ((flags & (FUTURE_MASKS_SERVER & ~POWER11_MASKS_SERVER)) != 0)
      return "future";
--- 5995,6001 ----
  
    /* Disable the flags that should never influence the .machine selection.  */
    flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT | OPTION_MASK_ISEL
! 	     | OPTION_MASK_ALTIVEC | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR);
  
    if ((flags & (FUTURE_MASKS_SERVER & ~POWER11_MASKS_SERVER)) != 0)
      return "future";
*************** rs6000_elf_declare_function_name (FILE *
*** 21527,21533 ****
    ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
    ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
  
!   if (TARGET_CMODEL == CMODEL_LARGE
        && rs6000_global_entry_point_prologue_needed_p ())
      {
        char buf[256];
--- 21530,21536 ----
    ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
    ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
  
!   if (TARGET_CMODEL == CMODEL_LARGE && !TARGET_PCREL
        && rs6000_global_entry_point_prologue_needed_p ())
      {
        char buf[256];
diff -Nrcpad gcc-16-20260822/gcc/config/rs6000/rs6000.md gcc-16-20260829/gcc/config/rs6000/rs6000.md
*** gcc-16-20260822/gcc/config/rs6000/rs6000.md	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/rs6000/rs6000.md	Sat Aug 29 22:32:06 2026
***************
*** 984,989 ****
--- 984,1058 ----
     (set_attr "length" "4,8")])
  
  
+ ;; On power10, optimize zero extending a QI/HI/SI/DImode value from memory that
+ ;; is going to a vector register target by generating a LXVR{B,H,W,D}X
+ ;; instruction without creating the TImode value in a GPR and using MTVSRDD to
+ ;; move it to the vector register.
+ (define_peephole2
+   [(set (match_operand:DI 0 "int_reg_operand")
+ 	(match_operand:DI 1 "memory_operand"))
+    (set (match_operand:DI 2 "base_reg_operand")
+ 	(const_int 0))
+    (set (match_operand:TI 3 "vsx_register_operand")
+ 	(match_operand:TI 4 "int_reg_operand"))]
+   "TARGET_POWER10 && TARGET_POWERPC64
+    && (reg_or_subregno (operands[0])
+        == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)
+    && (reg_or_subregno (operands[2])
+        == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)
+    && peep2_reg_dead_p (3, operands[4])
+    && (REG_P (XEXP (operands[1], 0))
+        || SUBREG_P (XEXP (operands[1], 0))
+        || GET_CODE (XEXP (operands[1], 0)) == PLUS)"
+   [(set (match_dup 3)
+ 	(zero_extend:TI (match_dup 5)))]
+ {
+   rtx mem = operands[1];
+   rtx addr = XEXP (mem, 0);
+ 
+   if (indexed_or_indirect_address (addr, DImode))
+     operands[5] = mem;
+   else
+     {
+       rtx op2 = operands[2];
+       emit_insn (gen_rtx_SET (op2, addr));
+       operands[5] = change_address (mem, DImode, op2);
+     }
+ })
+ 
+ (define_peephole2
+   [(set (match_operand:DI 0 "int_reg_operand")
+ 	(zero_extend:DI
+ 	 (match_operand:QHSI 1 "memory_operand")))
+    (set (match_operand:DI 2 "base_reg_operand")
+ 	(const_int 0))
+    (set (match_operand:TI 3 "vsx_register_operand")
+ 	(match_operand:TI 4 "int_reg_operand"))]
+   "TARGET_POWER10 && TARGET_POWERPC64
+    && (reg_or_subregno (operands[0])
+        == reg_or_subregno (operands[4]) + !!WORDS_BIG_ENDIAN)
+    && (reg_or_subregno (operands[2])
+        == reg_or_subregno (operands[4]) + !WORDS_BIG_ENDIAN)
+    && peep2_reg_dead_p (3, operands[4])
+    && (REG_P (XEXP (operands[1], 0))
+        || SUBREG_P (XEXP (operands[1], 0))
+        || GET_CODE (XEXP (operands[1], 0)) == PLUS)"
+   [(set (match_dup 3)
+ 	(zero_extend:TI (match_dup 5)))]
+ {
+   rtx mem = operands[1];
+   rtx addr = XEXP (mem, 0);
+ 
+   if (indexed_or_indirect_address (addr, DImode))
+     operands[5] = mem;
+   else
+     {
+       rtx op2 = operands[2];
+       emit_insn (gen_rtx_SET (op2, addr));
+       operands[5] = change_address (mem, DImode, op2);
+     }
+ })
+ 
  (define_insn "zero_extendsi<mode>2"
    [(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
  	(zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,?Z,?Z,r,wa,wa")))]
diff -Nrcpad gcc-16-20260822/gcc/config/rs6000/vsx.md gcc-16-20260829/gcc/config/rs6000/vsx.md
*** gcc-16-20260822/gcc/config/rs6000/vsx.md	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/config/rs6000/vsx.md	Sat Aug 29 22:32:06 2026
***************
*** 4829,4834 ****
--- 4829,4852 ----
    "lxvdsx %x0,%y1"
    [(set_attr "type" "vecload")])
  
+ ;; Optimize SPLAT of an extract from a V2DF/V2DI vector with a constant element
+ (define_insn "*vsx_splat_extract_<mode>"
+   [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
+ 	(vec_duplicate:VSX_D
+ 	 (vec_select:<VEC_base>
+ 	  (match_operand:VSX_D 1 "vsx_register_operand" "wa")
+ 	  (parallel [(match_operand 2 "const_0_to_1_operand" "n")]))))]
+   "VECTOR_MEM_VSX_P (<MODE>mode)"
+ {
+   int which_word = INTVAL (operands[2]);
+   if (!BYTES_BIG_ENDIAN)
+     which_word = 1 - which_word;
+ 
+   operands[3] = GEN_INT (which_word ? 3 : 0);
+   return "xxpermdi %x0,%x1,%x1,%3";
+ }
+   [(set_attr "type" "vecperm")])
+ 
  ;; V4SI splat support
  (define_insn "vsx_splat_v4si"
    [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
***************
*** 6296,6302 ****
     (SFBOOL_MFVSR_A		 3)		;; move to gpr src
     (SFBOOL_BOOL_D		 4)		;; and/ior/xor dest
     (SFBOOL_BOOL_A1		 5)		;; and/ior/xor arg1
!    (SFBOOL_BOOL_A2		 6)		;; and/ior/xor arg1
     (SFBOOL_SHL_D		 7)		;; shift left dest
     (SFBOOL_SHL_A		 8)		;; shift left arg
     (SFBOOL_MTVSR_D		 9)		;; move to vecter dest
--- 6314,6320 ----
     (SFBOOL_MFVSR_A		 3)		;; move to gpr src
     (SFBOOL_BOOL_D		 4)		;; and/ior/xor dest
     (SFBOOL_BOOL_A1		 5)		;; and/ior/xor arg1
!    (SFBOOL_BOOL_A2		 6)		;; and/ior/xor arg2
     (SFBOOL_SHL_D		 7)		;; shift left dest
     (SFBOOL_SHL_A		 8)		;; shift left arg
     (SFBOOL_MTVSR_D		 9)		;; move to vecter dest
***************
*** 6336,6353 ****
  ;; GPR, and instead move the integer mask value to the vector register after a
  ;; shift and do the VSX logical operation.
  
! ;; The insns for dealing with SFmode in GPR registers looks like:
  ;; (set (reg:V4SF reg2) (unspec:V4SF [(reg:SF reg1)] UNSPEC_VSX_CVDPSPN))
  ;;
! ;; (set (reg:DI reg3) (unspec:DI [(reg:V4SF reg2)] UNSPEC_P8V_RELOAD_FROM_VSX))
  ;;
! ;; (set (reg:DI reg4) (and:DI (reg:DI reg3) (reg:DI reg3)))
  ;;
  ;; (set (reg:DI reg5) (ashift:DI (reg:DI reg4) (const_int 32)))
  ;;
  ;; (set (reg:SF reg6) (unspec:SF [(reg:DI reg5)] UNSPEC_P8V_MTVSRD))
  ;;
! ;; (set (reg:SF reg6) (unspec:SF [(reg:SF reg6)] UNSPEC_VSX_CVSPDPN))
  
  (define_peephole2
    [(match_scratch:DI SFBOOL_TMP_GPR "r")
--- 6354,6371 ----
  ;; GPR, and instead move the integer mask value to the vector register after a
  ;; shift and do the VSX logical operation.
  
! ;; The insns for dealing with SFmode in GPR registers looks like on power8:
  ;; (set (reg:V4SF reg2) (unspec:V4SF [(reg:SF reg1)] UNSPEC_VSX_CVDPSPN))
  ;;
! ;; (set (reg:DI reg3) (zero_extend:DI (reg:SI reg2)))
  ;;
! ;; (set (reg:DI reg4) (and:SI (reg:SI reg3) (reg:SI mask)))
  ;;
  ;; (set (reg:DI reg5) (ashift:DI (reg:DI reg4) (const_int 32)))
  ;;
  ;; (set (reg:SF reg6) (unspec:SF [(reg:DI reg5)] UNSPEC_P8V_MTVSRD))
  ;;
! ;; (set (reg:SF reg7) (unspec:SF [(reg:SF reg6)] UNSPEC_VSX_CVSPDPN))
  
  (define_peephole2
    [(match_scratch:DI SFBOOL_TMP_GPR "r")
***************
*** 6428,6433 ****
--- 6446,6583 ----
    operands[SFBOOL_MTVSR_D_V4SF] = gen_rtx_REG (V4SFmode, regno_mtvsr_d);
  })
  
+ ;; Constants for SFbool optimization on power9/power10
+ (define_constants
+   [(SFBOOL2_TMP_VSX_V4SI	 0)		;; vector temporary (V4SI)
+    (SFBOOL2_TMP_GPR_SI		 1)		;; GPR temporary (SI)
+    (SFBOOL2_MFVSR_D		 2)		;; move to gpr dest (DI)
+    (SFBOOL2_MFVSR_A		 3)		;; move to gpr src (SI)
+    (SFBOOL2_BOOL_D		 4)		;; and/ior/xor dest (SI)
+    (SFBOOL2_BOOL_A1		 5)		;; and/ior/xor arg1 (SI)
+    (SFBOOL2_BOOL_A2		 6)		;; and/ior/xor arg2 (SI)
+    (SFBOOL2_SPLAT_D		 7)		;; splat dest (V4SI)
+    (SFBOOL2_MTVSR_D		 8)		;; move/splat to VSX dest.
+    (SFBOOL2_MTVSR_A		 9)		;; move/splat to VSX arg.
+    (SFBOOL2_MFVSR_A_V4SI	10)		;; MFVSR_A as V4SI
+    (SFBOOL2_MTVSR_D_V4SI	11)		;; MTVSR_D as V4SI
+    (SFBOOL2_XXSPLTW		12)])		;; 1 or 3 for XXSPLTW
+ 
+ ;; On power9/power10, the code is different because we have a splat 32-bit
+ ;; operation that does a direct move to the FPR/vector registers (MTVSRWS).
+ ;;
+ ;; The insns for dealing with SFmode in GPR registers looks like on
+ ;; power9/power10:
+ ;;
+ ;; (set (reg:V4SF reg2) (unspec:V4SF [(reg:SF reg1)] UNSPEC_VSX_CVDPSPN))
+ ;;
+ ;; (set (reg:DI reg3) (zero_extend:DI (reg:SI reg2)))
+ ;;
+ ;; (set (reg:SI reg4) (and:SI (reg:SI reg3) (reg:SI mask)))
+ ;;
+ ;; (set (reg:V4SI reg5) (vec_duplicate:V4SI (reg:SI reg4)))
+ ;;
+ ;; (set (reg:SF reg6) (unspec:SF [(reg:SF reg5)] UNSPEC_VSX_CVSPDPN))
+ 
+ ;; The VSX temporary needs to be an Altivec register in case we are trying to
+ ;; do and/ior/xor of -16..15 and we want to use VSPLTISW to load the constant.
+ ;;
+ ;; The GPR temporary is only used if we are trying to do a logical operation
+ ;; with a constant outside of the -16..15 range on a power9.  Otherwise, we can
+ ;; load the constant directly into the VSX temporary register.
+ 
+ (define_peephole2
+   [(match_scratch:V4SI SFBOOL2_TMP_VSX_V4SI "v")
+    (match_scratch:SI SFBOOL2_TMP_GPR_SI "r")
+ 
+    ;; Zero_extend and direct move
+    (set (match_operand:DI SFBOOL2_MFVSR_D "int_reg_operand")
+ 	(zero_extend:DI
+ 	 (match_operand:SI SFBOOL2_MFVSR_A "vsx_register_operand")))
+ 
+    ;; AND/IOR/XOR operation on int
+    (set (match_operand:SI SFBOOL2_BOOL_D "int_reg_operand")
+ 	(and_ior_xor:SI
+ 	 (match_operand:SI SFBOOL2_BOOL_A1 "int_reg_operand")
+ 	 (match_operand:SI SFBOOL2_BOOL_A2 "reg_or_cint_operand")))
+ 
+    ;; Splat sfbool result to vector register
+    (set (match_operand:V4SI SFBOOL2_SPLAT_D "vsx_register_operand")
+ 	(vec_duplicate:V4SI
+ 	 (match_dup SFBOOL2_BOOL_D)))]
+ 
+   "TARGET_POWERPC64 && TARGET_P9_VECTOR
+    && REG_P (operands[SFBOOL2_MFVSR_D])
+    && REG_P (operands[SFBOOL2_BOOL_A1])
+    && (REGNO (operands[SFBOOL2_MFVSR_D]) == REGNO (operands[SFBOOL2_BOOL_A1])
+        || (REG_P (operands[SFBOOL2_BOOL_A2])
+            && (REGNO (operands[SFBOOL2_MFVSR_D])
+                == REGNO (operands[SFBOOL2_BOOL_A2]))))
+    && peep2_reg_dead_p (3, operands[SFBOOL2_MFVSR_D])
+    && peep2_reg_dead_p (4, operands[SFBOOL2_BOOL_D])"
+ 
+   ;; Either (set (reg:SI xxx) (reg:SI yyy))	or
+   ;;        (set (reg:V4SI xxx) (const_vector (parallel [c, c, c, c])))
+   [(set (match_dup SFBOOL2_MTVSR_D)
+ 	(match_dup SFBOOL2_MTVSR_A))
+ 
+    ;; And/ior/xor on vector registers
+    (set (match_dup SFBOOL2_TMP_VSX_V4SI)
+ 	(and_ior_xor:V4SI
+ 	 (match_dup SFBOOL2_MFVSR_A_V4SI)
+ 	 (match_dup SFBOOL2_TMP_VSX_V4SI)))
+ 
+    ;; XXSPLTW t,r,r,1
+    (set (match_dup SFBOOL2_SPLAT_D)
+ 	(vec_duplicate:V4SI
+ 	 (vec_select:SI
+ 	  (match_dup SFBOOL2_TMP_VSX_V4SI)
+ 	  (parallel [(match_dup SFBOOL2_XXSPLTW)]))))]
+ {
+   rtx mfvsr_d = operands[SFBOOL2_MFVSR_D];
+   rtx bool_a1 = operands[SFBOOL2_BOOL_A1];
+   rtx bool_a2 = operands[SFBOOL2_BOOL_A2];
+   rtx bool_arg = (rtx_equal_p (mfvsr_d, bool_a1) ? bool_a2 : bool_a1);
+   int regno_mfvsr_a = REGNO (operands[SFBOOL2_MFVSR_A]);
+   int regno_tmp_vsx = REGNO (operands[SFBOOL2_TMP_VSX_V4SI]);
+ 
+   /* If the logical operation is a constant, form the constant in a vector
+      register.  */
+   if (CONST_INT_P (bool_arg))
+     {
+       HOST_WIDE_INT value = INTVAL (bool_arg);
+ 
+       /* See if we can directly load the constant, either by VSPLTIW or by
+          XXSPLTIW on power10.  */
+ 
+       if (IN_RANGE (value, -16, 15) || TARGET_PREFIXED)
+ 	{
+ 	  rtvec cv = gen_rtvec (4, bool_arg, bool_arg, bool_arg, bool_arg);
+ 	  operands[SFBOOL2_MTVSR_D] = gen_rtx_REG (V4SImode, regno_tmp_vsx);
+ 	  operands[SFBOOL2_MTVSR_A] = gen_rtx_CONST_VECTOR (V4SImode, cv);
+ 	}
+ 
+       else
+ 	{
+ 	  /* We need to load up the constant to a GPR and move it to a
+ 	     vector register.  */
+ 	  rtx tmp_gpr = operands[SFBOOL2_TMP_GPR_SI];
+ 	  emit_move_insn (tmp_gpr, bool_arg);
+ 	  operands[SFBOOL2_MTVSR_D] = gen_rtx_REG (SImode, regno_tmp_vsx);
+ 	  operands[SFBOOL2_MTVSR_A] = tmp_gpr;
+ 	}
+     }
+   else
+     {
+       /* Mask is in a register, move it to a vector register.  */
+       operands[SFBOOL2_MTVSR_D] = gen_rtx_REG (SImode, regno_tmp_vsx);
+       operands[SFBOOL2_MTVSR_A] = bool_arg;
+     }
+ 
+     operands[SFBOOL2_TMP_VSX_V4SI] = gen_rtx_REG (V4SImode, regno_tmp_vsx);
+     operands[SFBOOL2_MFVSR_A_V4SI] = gen_rtx_REG (V4SImode, regno_mfvsr_a);
+     operands[SFBOOL2_XXSPLTW] = GEN_INT (BYTES_BIG_ENDIAN ? 1 : 2);
+ })
+ 
  ;; Support signed/unsigned long long to float conversion vectorization.
  ;; Note that any_float (pc) here is just for code attribute <su>.
  (define_expand "vec_pack<su>_float_v2di"
diff -Nrcpad gcc-16-20260822/gcc/cp/ChangeLog gcc-16-20260829/gcc/cp/ChangeLog
*** gcc-16-20260822/gcc/cp/ChangeLog	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/cp/ChangeLog	Sat Aug 29 22:32:07 2026
***************
*** 1,3 ****
--- 1,17 ----
+ 2026-08-24  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-08-22  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/124888
+ 	* pt.cc (tsubst_expr): Pass type to {get,build}_typeid.
+ 	* rtti.cc (build_typeid, get_typeid): Take it.
+ 	(type_info_ptr_type): Remove.
+ 	(get_tinfo_ptr): Take tinfo_ptr_type instead of voidp.
+ 	(get_tinfo_ptr_dynamic): Likewise.
+ 	(get_void_tinfo_ptr): Pass const_ptr_type_node.
+ 	* cp-tree.h (build_typeid, get_typeid): Adjust.
+ 
  2026-08-20  Marek Polacek  <polacek@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260822/gcc/cp/cp-tree.h gcc-16-20260829/gcc/cp/cp-tree.h
*** gcc-16-20260822/gcc/cp/cp-tree.h	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/cp/cp-tree.h	Sat Aug 29 22:32:07 2026
*************** extern tree convert_reflect_constant_arg
*** 8383,8392 ****
  extern GTY(()) vec<tree, va_gc> *unemitted_tinfo_decls;
  
  extern void init_rtti_processing		(void);
! extern tree build_typeid			(tree, tsubst_flags_t);
  extern tree get_tinfo_decl_direct	        (tree, tree, int);
  extern tree get_tinfo_decl			(tree);
! extern tree get_typeid				(tree, tsubst_flags_t);
  extern tree build_headof			(tree);
  extern tree build_dynamic_cast			(location_t, tree, tree,
  						 tsubst_flags_t);
--- 8383,8392 ----
  extern GTY(()) vec<tree, va_gc> *unemitted_tinfo_decls;
  
  extern void init_rtti_processing		(void);
! extern tree build_typeid			(tree, tsubst_flags_t, tree = NULL_TREE);
  extern tree get_tinfo_decl_direct	        (tree, tree, int);
  extern tree get_tinfo_decl			(tree);
! extern tree get_typeid				(tree, tsubst_flags_t, tree = NULL_TREE);
  extern tree build_headof			(tree);
  extern tree build_dynamic_cast			(location_t, tree, tree,
  						 tsubst_flags_t);
diff -Nrcpad gcc-16-20260822/gcc/cp/pt.cc gcc-16-20260829/gcc/cp/pt.cc
*** gcc-16-20260822/gcc/cp/pt.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/cp/pt.cc	Sat Aug 29 22:32:07 2026
*************** tsubst_expr (tree t, tree args, tsubst_f
*** 22928,22939 ****
  	if (TYPE_P (operand_0))
  	  {
  	    operand_0 = tsubst (operand_0, args, complain, in_decl);
! 	    RETURN (get_typeid (operand_0, complain));
  	  }
  	else
  	  {
  	    operand_0 = RECUR (operand_0);
! 	    RETURN (build_typeid (operand_0, complain));
  	  }
        }
  
--- 22928,22939 ----
  	if (TYPE_P (operand_0))
  	  {
  	    operand_0 = tsubst (operand_0, args, complain, in_decl);
! 	    RETURN (get_typeid (operand_0, complain, TREE_TYPE (t)));
  	  }
  	else
  	  {
  	    operand_0 = RECUR (operand_0);
! 	    RETURN (build_typeid (operand_0, complain, TREE_TYPE (t)));
  	  }
        }
  
diff -Nrcpad gcc-16-20260822/gcc/cp/rtti.cc gcc-16-20260829/gcc/cp/rtti.cc
*** gcc-16-20260822/gcc/cp/rtti.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/cp/rtti.cc	Sat Aug 29 22:32:07 2026
*************** throw_bad_typeid (void)
*** 222,252 ****
    return build_cxx_call (fn, 0, NULL, tf_warning_or_error);
  }
  
- /* const type_info*.  */
- 
- inline tree
- type_info_ptr_type ()
- {
-   return build_pointer_type (const_type_info_type_node);
- }
- 
  /* Return a pointer to a type_info object describing TYPE, suitably
     cast to the language defined type (for typeid) or void (for building
     up the descriptors).  */
  
  static tree
! get_tinfo_ptr (tree type, bool voidp = false)
  {
    tree decl = get_tinfo_decl (type);
    mark_used (decl);
  
!   tree ptype = voidp ? const_ptr_type_node : type_info_ptr_type ();
!   return build_nop (ptype, build_address (decl));
  }
  static inline tree
  get_void_tinfo_ptr (tree type)
  {
!   return get_tinfo_ptr (type, true);
  }
  
  /* Return an lvalue expression whose type is "const std::type_info"
--- 222,243 ----
    return build_cxx_call (fn, 0, NULL, tf_warning_or_error);
  }
  
  /* Return a pointer to a type_info object describing TYPE, suitably
     cast to the language defined type (for typeid) or void (for building
     up the descriptors).  */
  
  static tree
! get_tinfo_ptr (tree type, tree tinfo_ptr_type)
  {
    tree decl = get_tinfo_decl (type);
    mark_used (decl);
  
!   return build_nop (tinfo_ptr_type, build_address (decl));
  }
  static inline tree
  get_void_tinfo_ptr (tree type)
  {
!   return get_tinfo_ptr (type, const_ptr_type_node);
  }
  
  /* Return an lvalue expression whose type is "const std::type_info"
*************** get_void_tinfo_ptr (tree type)
*** 255,261 ****
     otherwise return the static type of the expression.  */
  
  static tree
! get_tinfo_ptr_dynamic (tree exp, tsubst_flags_t complain)
  {
    tree type;
    tree t;
--- 246,252 ----
     otherwise return the static type of the expression.  */
  
  static tree
! get_tinfo_ptr_dynamic (tree exp, tsubst_flags_t complain, tree tinfo_ptr_type)
  {
    tree type;
    tree t;
*************** get_tinfo_ptr_dynamic (tree exp, tsubst_
*** 291,301 ****
        index = build_int_cst (NULL_TREE,
  			     -1 * TARGET_VTABLE_DATA_ENTRY_DISTANCE);
        t = build_vtbl_ref (exp, index);
!       t = convert (type_info_ptr_type (), t);
      }
    else
      /* Otherwise return the type_info for the static type of the expr.  */
!     t = get_tinfo_ptr (type);
  
    return t;
  }
--- 282,292 ----
        index = build_int_cst (NULL_TREE,
  			     -1 * TARGET_VTABLE_DATA_ENTRY_DISTANCE);
        t = build_vtbl_ref (exp, index);
!       t = convert (tinfo_ptr_type, t);
      }
    else
      /* Otherwise return the type_info for the static type of the expr.  */
!     t = get_tinfo_ptr (type, tinfo_ptr_type);
  
    return t;
  }
*************** typeid_ok_p (void)
*** 344,359 ****
     an lvalue of type "const std::type_info".  */
  
  tree
! build_typeid (tree exp, tsubst_flags_t complain)
  {
    tree cond = NULL_TREE, initial_expr = exp;
    int nonnull = 0;
  
!   if (exp == error_mark_node || !typeid_ok_p ())
      return error_mark_node;
  
    if (processing_template_decl)
!     return build_min (TYPEID_EXPR, const_type_info_type_node, exp);
  
    if (CLASS_TYPE_P (TREE_TYPE (exp))
        && TYPE_POLYMORPHIC_P (TREE_TYPE (exp))
--- 335,357 ----
     an lvalue of type "const std::type_info".  */
  
  tree
! build_typeid (tree exp, tsubst_flags_t complain, tree tinfo_type/*=NULL_TREE*/)
  {
    tree cond = NULL_TREE, initial_expr = exp;
    int nonnull = 0;
  
!   if (exp == error_mark_node)
      return error_mark_node;
  
+   if (!tinfo_type)
+     {
+       if (!typeid_ok_p ())
+ 	return error_mark_node;
+       tinfo_type = const_type_info_type_node;
+     }
+ 
    if (processing_template_decl)
!     return build_min (TYPEID_EXPR, tinfo_type, exp);
  
    if (CLASS_TYPE_P (TREE_TYPE (exp))
        && TYPE_POLYMORPHIC_P (TREE_TYPE (exp))
*************** build_typeid (tree exp, tsubst_flags_t c
*** 368,374 ****
        exp = cp_build_fold_indirect_ref (exp);
      }
  
!   exp = get_tinfo_ptr_dynamic (exp, complain);
  
    if (exp == error_mark_node)
      return error_mark_node;
--- 366,373 ----
        exp = cp_build_fold_indirect_ref (exp);
      }
  
!   exp = get_tinfo_ptr_dynamic (exp, complain,
! 			       build_pointer_type (tinfo_type));
  
    if (exp == error_mark_node)
      return error_mark_node;
*************** get_tinfo_decl_direct (tree type, tree n
*** 502,514 ****
  /* Return the type_info object for TYPE.  */
  
  tree
! get_typeid (tree type, tsubst_flags_t complain)
  {
!   if (type == error_mark_node || !typeid_ok_p ())
      return error_mark_node;
  
    if (processing_template_decl)
!     return build_min (TYPEID_EXPR, const_type_info_type_node, type);
  
    /* If the type of the type-id is a reference type, the result of the
       typeid expression refers to a type_info object representing the
--- 501,520 ----
  /* Return the type_info object for TYPE.  */
  
  tree
! get_typeid (tree type, tsubst_flags_t complain, tree tinfo_type/*=NULL_TREE*/)
  {
!   if (type == error_mark_node)
      return error_mark_node;
  
+   if (!tinfo_type)
+     {
+       if (!typeid_ok_p ())
+ 	return error_mark_node;
+       tinfo_type = const_type_info_type_node;
+     }
+ 
    if (processing_template_decl)
!     return build_min (TYPEID_EXPR, tinfo_type, type);
  
    /* If the type of the type-id is a reference type, the result of the
       typeid expression refers to a type_info object representing the
*************** get_typeid (tree type, tsubst_flags_t co
*** 537,543 ****
    if (!type)
      return error_mark_node;
  
!   return cp_build_fold_indirect_ref (get_tinfo_ptr (type));
  }
  
  /* Check whether TEST is null before returning RESULT.  If TEST is used in
--- 543,550 ----
    if (!type)
      return error_mark_node;
  
!   tinfo_type = build_pointer_type (tinfo_type);
!   return cp_build_fold_indirect_ref (get_tinfo_ptr (type, tinfo_type));
  }
  
  /* Check whether TEST is null before returning RESULT.  If TEST is used in
diff -Nrcpad gcc-16-20260822/gcc/doc/md.texi gcc-16-20260829/gcc/doc/md.texi
*** gcc-16-20260822/gcc/doc/md.texi	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/doc/md.texi	Sat Aug 29 22:32:07 2026
*************** The operation is equivalent to:
*** 7391,7397 ****
  
  @smallexample
  int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
! for (j = 0; j < operand4 + operand5; j++)
    for (i = 0; i < c; i++)
      if (operand2[j])
        operand0[i][j] = operand1[j * c + i];
--- 7391,7397 ----
  
  @smallexample
  int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
! for (j = 0; j < operand4 - operand5; j++)
    for (i = 0; i < c; i++)
      if (operand2[j])
        operand0[i][j] = operand1[j * c + i];
*************** The operation is equivalent to:
*** 7443,7449 ****
  
  @smallexample
  int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
! for (j = 0; j < operand3 + operand4; j++)
    if (operand2[j])
      for (i = 0; i < c; i++)
        operand0[j * c + i] = operand1[i][j];
--- 7443,7449 ----
  
  @smallexample
  int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
! for (j = 0; j < operand3 - operand4; j++)
    if (operand2[j])
      for (i = 0; i < c; i++)
        operand0[j * c + i] = operand1[i][j];
*************** Like @samp{gather_load@var{m}@var{n}}, b
*** 7490,7500 ****
  (operand 7) and a bias operand (operand 8).
  
  Similar to mask_len_load the instruction loads at
! most (operand 7 + operand 8) elements from memory.
  Bit @var{i} of the mask is set if element @var{i} of the result should
  be loaded from memory and clear if element @var{i} of the result should
  be set to element @var{i} of operand 6.
! Mask elements @var{i} with @var{i} > (operand 7 + operand 8) are ignored.
  
  @mdindex mask_len_strided_load@var{m}
  @item @samp{mask_len_strided_load@var{m}}
--- 7490,7500 ----
  (operand 7) and a bias operand (operand 8).
  
  Similar to mask_len_load the instruction loads at
! most (operand 7 - operand 8) elements from memory.
  Bit @var{i} of the mask is set if element @var{i} of the result should
  be loaded from memory and clear if element @var{i} of the result should
  be set to element @var{i} of operand 6.
! Mask elements @var{i} with @var{i} > (operand 7 - operand 8) are ignored.
  
  @mdindex mask_len_strided_load@var{m}
  @item @samp{mask_len_strided_load@var{m}}
*************** operand 3 is mask operand, operand 4 is
*** 7505,7514 ****
  The instruction can be seen as a special case of @code{mask_len_gather_load@var{m}@var{n}}
  with an offset vector that is a @code{vec_series} with zero as base and operand 2 as step.
  For each element the load address is operand 1 + @var{i} * operand 2.
! Similar to mask_len_load, the instruction loads at most (operand 4 + operand 5) elements from memory.
  Element @var{i} of the mask (operand 3) is set if element @var{i} of the result should
  be loaded from memory and clear if element @var{i} of the result should be zero.
! Mask elements @var{i} with @var{i} > (operand 4 + operand 5) are ignored.
  
  @mdindex scatter_store@var{m}@var{n}
  @item @samp{scatter_store@var{m}@var{n}}
--- 7505,7514 ----
  The instruction can be seen as a special case of @code{mask_len_gather_load@var{m}@var{n}}
  with an offset vector that is a @code{vec_series} with zero as base and operand 2 as step.
  For each element the load address is operand 1 + @var{i} * operand 2.
! Similar to mask_len_load, the instruction loads at most (operand 4 - operand 5) elements from memory.
  Element @var{i} of the mask (operand 3) is set if element @var{i} of the result should
  be loaded from memory and clear if element @var{i} of the result should be zero.
! Mask elements @var{i} with @var{i} > (operand 4 - operand 5) are ignored.
  
  @mdindex scatter_store@var{m}@var{n}
  @item @samp{scatter_store@var{m}@var{n}}
*************** of the result should be stored to memory
*** 7543,7551 ****
  @item @samp{mask_len_scatter_store@var{m}@var{n}}
  Like @samp{scatter_store@var{m}@var{n}}, but takes an extra mask operand (operand 5),
  a len operand (operand 6) as well as a bias operand (operand 7).  The instruction stores
! at most (operand 6 + operand 7) elements of (operand 4) to memory.
  Bit @var{i} of the mask is set if element @var{i} of (operand 4) should be stored.
! Mask elements @var{i} with @var{i} > (operand 6 + operand 7) are ignored.
  
  @mdindex mask_len_strided_store@var{m}
  @item @samp{mask_len_strided_store@var{m}}
--- 7543,7551 ----
  @item @samp{mask_len_scatter_store@var{m}@var{n}}
  Like @samp{scatter_store@var{m}@var{n}}, but takes an extra mask operand (operand 5),
  a len operand (operand 6) as well as a bias operand (operand 7).  The instruction stores
! at most (operand 6 - operand 7) elements of (operand 4) to memory.
  Bit @var{i} of the mask is set if element @var{i} of (operand 4) should be stored.
! Mask elements @var{i} with @var{i} > (operand 6 - operand 7) are ignored.
  
  @mdindex mask_len_strided_store@var{m}
  @item @samp{mask_len_strided_store@var{m}}
*************** operand 3 is mask operand, operand 4 is
*** 7556,7564 ****
  The instruction can be seen as a special case of @code{mask_len_scatter_store@var{m}@var{n}}
  with an offset vector that is a @code{vec_series} with zero as base and operand 1 as step.
  For each element the store address is operand 0 + @var{i} * operand 1.
! Similar to mask_len_store, the instruction stores at most (operand 4 + operand 5) elements of
  mask (operand 3) to memory.  Element @var{i} of the mask is set if element @var{i} of (operand 3)
! should be stored.  Mask elements @var{i} with @var{i} > (operand 4 + operand 5) are ignored.
  
  @mdindex while_ult@var{m}@var{n}
  @item @code{while_ult@var{m}@var{n}}
--- 7556,7564 ----
  The instruction can be seen as a special case of @code{mask_len_scatter_store@var{m}@var{n}}
  with an offset vector that is a @code{vec_series} with zero as base and operand 1 as step.
  For each element the store address is operand 0 + @var{i} * operand 1.
! Similar to mask_len_store, the instruction stores at most (operand 4 - operand 5) elements of
  mask (operand 3) to memory.  Element @var{i} of the mask is set if element @var{i} of (operand 3)
! should be stored.  Mask elements @var{i} with @var{i} > (operand 4 - operand 5) are ignored.
  
  @mdindex while_ult@var{m}@var{n}
  @item @code{while_ult@var{m}@var{n}}
*************** This pattern is not allowed to @code{FAI
*** 7768,7774 ****
  
  @mdindex len_load_@var{m}
  @item @samp{len_load_@var{m}}
! Load (operand 3 + operand 4) elements from memory operand 1
  into vector register operand 0.  Operands 0 and 1 have mode @var{m},
  which must be a vector mode.  Operand 3 has whichever integer mode the
  target prefers.  Operand 2 (the ``else value'') is of mode @var{m} and
--- 7768,7774 ----
  
  @mdindex len_load_@var{m}
  @item @samp{len_load_@var{m}}
! Load (operand 3 - operand 4) elements from memory operand 1
  into vector register operand 0.  Operands 0 and 1 have mode @var{m},
  which must be a vector mode.  Operand 3 has whichever integer mode the
  target prefers.  Operand 2 (the ``else value'') is of mode @var{m} and
*************** constant bias: it is either a constant 0
*** 7781,7787 ****
  operand 4 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 3 + operand 4) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes rather than
--- 7781,7787 ----
  operand 4 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 3 - operand 4) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes rather than
*************** This pattern is not allowed to @code{FAI
*** 7792,7798 ****
  
  @mdindex len_store_@var{m}
  @item @samp{len_store_@var{m}}
! Store (operand 2 + operand 3) vector elements from vector register operand 1
  into memory operand 0, leaving the other elements of
  operand 0 unchanged.  Operands 0 and 1 have mode @var{m}, which must be
  a vector mode.  Operand 2 has whichever integer mode the target prefers.
--- 7792,7798 ----
  
  @mdindex len_store_@var{m}
  @item @samp{len_store_@var{m}}
! Store (operand 2 - operand 3) vector elements from vector register operand 1
  into memory operand 0, leaving the other elements of
  operand 0 unchanged.  Operands 0 and 1 have mode @var{m}, which must be
  a vector mode.  Operand 2 has whichever integer mode the target prefers.
*************** constant bias: it is either a constant 0
*** 7803,7809 ****
  operand 3 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 2 + operand 3) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes
--- 7803,7809 ----
  operand 3 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 2 - operand 3) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes
*************** This pattern is not allowed to @code{FAI
*** 7815,7837 ****
  @mdindex mask_len_load@var{m}@var{n}
  @item @samp{mask_len_load@var{m}@var{n}}
  Perform a masked load from the memory location pointed to by operand 1
! into register operand 0.  (operand 3 + operand 4) elements are loaded from
  memory and other elements in operand 0 are set to undefined values.
  This is a combination of len_load and maskload.
  Operands 0 and 1 have mode @var{m}, which must be a vector mode.  Operand 3
  has whichever integer mode the target prefers.  A mask is specified in
  operand 2 which must be of type @var{n}.  The mask has lower precedence than
  the length and is itself subject to length masking,
! i.e. only mask indices < (operand 4 + operand 5) are used.
  Operand 3 is an else operand similar to the one in @code{maskload}.
! Operand 4 conceptually has mode @code{QI}.
  
  Operand 4 can be a variable or a constant amount.  Operand 5 specifies a
  constant bias: it is either a constant 0 or a constant -1.  The predicate on
  operand 5 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 4 + operand 5) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes
--- 7815,7837 ----
  @mdindex mask_len_load@var{m}@var{n}
  @item @samp{mask_len_load@var{m}@var{n}}
  Perform a masked load from the memory location pointed to by operand 1
! into register operand 0.  (operand 4 - operand 5) elements are loaded from
  memory and other elements in operand 0 are set to undefined values.
  This is a combination of len_load and maskload.
  Operands 0 and 1 have mode @var{m}, which must be a vector mode.  Operand 3
  has whichever integer mode the target prefers.  A mask is specified in
  operand 2 which must be of type @var{n}.  The mask has lower precedence than
  the length and is itself subject to length masking,
! i.e. only mask indices < (operand 4 - operand 5) are used.
  Operand 3 is an else operand similar to the one in @code{maskload}.
! Operand 5 conceptually has mode @code{QI}.
  
  Operand 4 can be a variable or a constant amount.  Operand 5 specifies a
  constant bias: it is either a constant 0 or a constant -1.  The predicate on
  operand 5 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 4 - operand 5) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes
*************** This pattern is not allowed to @code{FAI
*** 7843,7855 ****
  @mdindex mask_len_store@var{m}@var{n}
  @item @samp{mask_len_store@var{m}@var{n}}
  Perform a masked store from vector register operand 1 into memory operand 0.
! (operand 3 + operand 4) elements are stored to memory
  and leave the other elements of operand 0 unchanged.
  This is a combination of len_store and maskstore.
  Operands 0 and 1 have mode @var{m}, which must be a vector mode.  Operand 3 has whichever
  integer mode the target prefers.  A mask is specified in operand 2 which must be
  of type @var{n}.  The mask has lower precedence than the length and is itself subject to
! length masking, i.e. only mask indices < (operand 3 + operand 4) are used.
  Operand 4 conceptually has mode @code{QI}.
  
  Operand 2 can be a variable or a constant amount.  Operand 3 specifies a
--- 7843,7855 ----
  @mdindex mask_len_store@var{m}@var{n}
  @item @samp{mask_len_store@var{m}@var{n}}
  Perform a masked store from vector register operand 1 into memory operand 0.
! (operand 3 - operand 4) elements are stored to memory
  and leave the other elements of operand 0 unchanged.
  This is a combination of len_store and maskstore.
  Operands 0 and 1 have mode @var{m}, which must be a vector mode.  Operand 3 has whichever
  integer mode the target prefers.  A mask is specified in operand 2 which must be
  of type @var{n}.  The mask has lower precedence than the length and is itself subject to
! length masking, i.e. only mask indices < (operand 3 - operand 4) are used.
  Operand 4 conceptually has mode @code{QI}.
  
  Operand 2 can be a variable or a constant amount.  Operand 3 specifies a
*************** constant bias: it is either a constant 0
*** 7857,7863 ****
  operand 4 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 2 + operand 4) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes
--- 7857,7863 ----
  operand 4 must only accept the bias values that the target actually supports.
  GCC handles a bias of 0 more efficiently than a bias of -1.
  
! If (operand 3 - operand 4) exceeds the number of elements in mode
  @var{m}, the behavior is undefined.
  
  If the target prefers the length to be measured in bytes
*************** for (i = 0; i < GET_MODE_NUNITS (@var{m}
*** 8604,8616 ****
  @itemx @samp{cond_len_floor@var{mode}}
  @itemx @samp{cond_len_round@var{mode}}
  @itemx @samp{cond_len_rint@var{mode}}
! When operand 1 is true and element index < operand 4 + operand 5, perform an operation on operands 1 and
  store the result in operand 0, otherwise store operand 2 in operand 0.
  The operation only works for the operands are vectors.
  
  @smallexample
  for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
!   op0[i] = (i < ops[4] + ops[5] && op1[i]
              ? @var{op} op2[i]
              : op3[i]);
  @end smallexample
--- 8604,8616 ----
  @itemx @samp{cond_len_floor@var{mode}}
  @itemx @samp{cond_len_round@var{mode}}
  @itemx @samp{cond_len_rint@var{mode}}
! When operand 1 is true and element index < operand 4 - operand 5, perform an operation on operands 1 and
  store the result in operand 0, otherwise store operand 2 in operand 0.
  The operation only works for the operands are vectors.
  
  @smallexample
  for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
!   op0[i] = (i < ops[4] - ops[5] && op1[i]
              ? @var{op} op2[i]
              : op3[i]);
  @end smallexample
*************** form of @samp{@var{op}@var{mode}2}.
*** 8670,8682 ****
  @itemx @samp{cond_len_ashl@var{mode}}
  @itemx @samp{cond_len_ashr@var{mode}}
  @itemx @samp{cond_len_lshr@var{mode}}
! When operand 1 is true and element index < operand 5 + operand 6, perform an operation on operands 2 and 3 and
  store the result in operand 0, otherwise store operand 4 in operand 0.
  The operation only works for the operands are vectors.
  
  @smallexample
  for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
!   op0[i] = (i < ops[5] + ops[6] && op1[i]
              ? op2[i] @var{op} op3[i]
              : op4[i]);
  @end smallexample
--- 8670,8682 ----
  @itemx @samp{cond_len_ashl@var{mode}}
  @itemx @samp{cond_len_ashr@var{mode}}
  @itemx @samp{cond_len_lshr@var{mode}}
! When operand 1 is true and element index < operand 5 - operand 6, perform an operation on operands 2 and 3 and
  store the result in operand 0, otherwise store operand 4 in operand 0.
  The operation only works for the operands are vectors.
  
  @smallexample
  for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
!   op0[i] = (i < ops[5] - ops[6] && op1[i]
              ? op2[i] @var{op} op3[i]
              : op4[i]);
  @end smallexample
*************** takes 3 operands rather than two.  For e
*** 8713,8719 ****
  
  @smallexample
  for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
!   op0[i] = (i < ops[6] + ops[7] && op1[i]
              ? fma (op2[i], op3[i], op4[i])
              : op5[i]);
  @end smallexample
--- 8713,8719 ----
  
  @smallexample
  for (i = 0; i < GET_MODE_NUNITS (@var{m}); i++)
!   op0[i] = (i < ops[6] - ops[7] && op1[i]
              ? fma (op2[i], op3[i], op4[i])
              : op5[i]);
  @end smallexample
diff -Nrcpad gcc-16-20260822/gcc/doc/riscv-mcpu.texi gcc-16-20260829/gcc/doc/riscv-mcpu.texi
*** gcc-16-20260822/gcc/doc/riscv-mcpu.texi	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/doc/riscv-mcpu.texi	Sat Aug 29 22:32:07 2026
*************** by particular CPU name. Permissible valu
*** 64,69 ****
--- 64,71 ----
  
  @samp{tt-ascalon-d8},
  
+ @samp{tt-ascalon-xg},
+ 
  @samp{xiangshan-nanhu},
  
  @samp{xiangshan-kunminghu},
diff -Nrcpad gcc-16-20260822/gcc/doc/riscv-mtune.texi gcc-16-20260829/gcc/doc/riscv-mtune.texi
*** gcc-16-20260822/gcc/doc/riscv-mtune.texi	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/doc/riscv-mtune.texi	Sat Aug 29 22:32:07 2026
*************** particular CPU name.  Permissible values
*** 32,37 ****
--- 32,39 ----
  
  @samp{tt-ascalon-x},
  
+ @samp{tt-ascalon-xg},
+ 
  @samp{tt-ascalon-d8},
  
  @samp{thead-c906},
diff -Nrcpad gcc-16-20260822/gcc/ext-dce.cc gcc-16-20260829/gcc/ext-dce.cc
*** gcc-16-20260822/gcc/ext-dce.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/ext-dce.cc	Sat Aug 29 22:32:07 2026
*************** carry_backpropagate (unsigned HOST_WIDE_
*** 571,577 ****
    if (mask == 0)
      return 0;
  
!   enum machine_mode mode = GET_MODE_INNER (GET_MODE (x));
    unsigned HOST_WIDE_INT mmask = GET_MODE_MASK (mode);
  
    /* While we don't try to optimize operations on types larger
--- 571,593 ----
    if (mask == 0)
      return 0;
  
!   /* Consider a vector operation, the bits live are the element bits live
!      broadcasted across the vector.  So there can be holes (consider a
!      logical shift).
! 
!      Vector modes aren't likely to represent cases we can optimize with
!      any regularity.  It seems sensible to just punt that case in a
!      conservatively correct way.
! 
!      The conservatively corect choice here would be to return the mode
!      mask for the outer mode.  We're already doing that for modes larger
!      than HOST_BITS_PER_WIDE_INT, so it should be safe for larger vectors
!      as well as something like V2HI.  */
!   if (VECTOR_MODE_P (GET_MODE (x)) || COMPLEX_MODE_P (GET_MODE (x)))
!     return GET_MODE_MASK (GET_MODE (x));
!     
! 
!   enum machine_mode mode = GET_MODE (x);
    unsigned HOST_WIDE_INT mmask = GET_MODE_MASK (mode);
  
    /* While we don't try to optimize operations on types larger
*************** carry_backpropagate (unsigned HOST_WIDE_
*** 645,650 ****
--- 661,671 ----
  	  || !GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))).is_constant ())
  	return -1;
  
+       /* See note about vector modes near the start of this function.  */
+       if (VECTOR_MODE_P (GET_MODE (XEXP (x, 0)))
+ 	  || COMPLEX_MODE_P (GET_MODE (XEXP (x, 0))))
+ 	return GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
+ 
        /* We want the mode of the inner object.  We need to ensure its
  	 sign bit is on in MASK.  */
        mode = GET_MODE_INNER (GET_MODE (XEXP (x, 0)));
*************** ext_dce_process_uses (rtx_insn *insn, rt
*** 780,786 ****
  		{
  		  rtx inner = XEXP (src, 0);
  		  unsigned HOST_WIDE_INT src_mask
! 		    = GET_MODE_MASK (GET_MODE_INNER (GET_MODE (inner)));
  
  		  /* DST_MASK could be zero if we had something in the SET
  		     that we couldn't handle.  */
--- 801,807 ----
  		{
  		  rtx inner = XEXP (src, 0);
  		  unsigned HOST_WIDE_INT src_mask
! 		    = GET_MODE_MASK (GET_MODE (inner));
  
  		  /* DST_MASK could be zero if we had something in the SET
  		     that we couldn't handle.  */
*************** ext_dce_process_uses (rtx_insn *insn, rt
*** 937,944 ****
  			 propagate destination liveness through, then just
  			 set the mask to the mode's mask.  */
  		      if (!safe_for_live_propagation (code))
! 			tmp_mask
! 			  = GET_MODE_MASK (GET_MODE_INNER (GET_MODE (y)));
  
  		      if (tmp_mask & 0xff)
  			bitmap_set_bit (livenow, rn);
--- 958,964 ----
  			 propagate destination liveness through, then just
  			 set the mask to the mode's mask.  */
  		      if (!safe_for_live_propagation (code))
! 			tmp_mask = GET_MODE_MASK (GET_MODE (y));
  
  		      if (tmp_mask & 0xff)
  			bitmap_set_bit (livenow, rn);
diff -Nrcpad gcc-16-20260822/gcc/fortran/ChangeLog gcc-16-20260829/gcc/fortran/ChangeLog
*** gcc-16-20260822/gcc/fortran/ChangeLog	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/fortran/ChangeLog	Sat Aug 29 22:32:07 2026
***************
*** 1,3 ****
--- 1,36 ----
+ 2026-08-25  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-08-09  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/98573
+ 	* trans-array.cc (gfc_array_init_size): If the expr3_desc is an
+ 	array descriptor, use it for 'type'.
+ 	* trans-stmt.cc (gfc_trans_allocate): Use trans_assignment to
+ 	assign the source for class sources.
+ 
+ 2026-08-24  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-03  Steven G. Kargl  <kargl@gcc.gnu.org>
+ 
+ 	PR fortran/105594
+ 	* module.cc (gfc_use_module): Suppress bogus warning for a missing
+ 	ONLY clause on a submodule.
+ 
+ 2026-08-24  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-02  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/88632
+ 	PR fortran/104630
+ 	* module.cc (write_symtree): Do not filter out private symbols
+ 	when writing a submodule interface file (.smod).  Submodules are
+ 	descendants of their ancestor module and access private symbols
+ 	in the module's contains section via host association per
+ 	Fortran 2018 section 14.2.2.
+ 
  2026-08-18  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260822/gcc/fortran/module.cc gcc-16-20260829/gcc/fortran/module.cc
*** gcc-16-20260822/gcc/fortran/module.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/fortran/module.cc	Sat Aug 29 22:32:07 2026
*************** write_symtree (gfc_symtree *st)
*** 6666,6672 ****
  	&& sym->ns->proc_name->attr.if_source == IFSRC_IFBODY)
      return;
  
!   if (!gfc_check_symbol_access (sym)
        || (sym->attr.flavor == FL_PROCEDURE && sym->attr.generic
  	  && !sym->attr.subroutine && !sym->attr.function))
      return;
--- 6666,6673 ----
  	&& sym->ns->proc_name->attr.if_source == IFSRC_IFBODY)
      return;
  
!   if ((!gfc_check_symbol_access (sym)
!        && (!sym->attr.public_used || submodule_name == NULL))
        || (sym->attr.flavor == FL_PROCEDURE && sym->attr.generic
  	  && !sym->attr.subroutine && !sym->attr.function))
      return;
*************** gfc_use_module (gfc_use_list *module)
*** 7693,7699 ****
    only_flag = module->only_flag;
    current_intmod = INTMOD_NONE;
  
!   if (!only_flag)
      gfc_warning_now (OPT_Wuse_without_only,
  		     "USE statement at %C has no ONLY qualifier");
  
--- 7694,7700 ----
    only_flag = module->only_flag;
    current_intmod = INTMOD_NONE;
  
!   if (!only_flag && gfc_state_stack->state != COMP_SUBMODULE)
      gfc_warning_now (OPT_Wuse_without_only,
  		     "USE statement at %C has no ONLY qualifier");
  
diff -Nrcpad gcc-16-20260822/gcc/fortran/trans-array.cc gcc-16-20260829/gcc/fortran/trans-array.cc
*** gcc-16-20260822/gcc/fortran/trans-array.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/fortran/trans-array.cc	Sat Aug 29 22:32:07 2026
*************** gfc_array_init_size (tree descriptor, in
*** 6495,6501 ****
    gfc_se se;
    int n;
  
!   type = TREE_TYPE (descriptor);
  
    stride = gfc_index_one_node;
    offset = gfc_index_zero_node;
--- 6495,6507 ----
    gfc_se se;
    int n;
  
!   if (expr->ts.type == BT_CLASS
!       && expr3_desc != NULL_TREE
!       && GFC_DESCRIPTOR_TYPE_P (TREE_TYPE (expr3_desc)))
!     type = TREE_TYPE (expr3_desc);
!   else
!     type = TREE_TYPE (descriptor);
! 
  
    stride = gfc_index_one_node;
    offset = gfc_index_zero_node;
diff -Nrcpad gcc-16-20260822/gcc/fortran/trans-stmt.cc gcc-16-20260829/gcc/fortran/trans-stmt.cc
*** gcc-16-20260822/gcc/fortran/trans-stmt.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/fortran/trans-stmt.cc	Sat Aug 29 22:32:07 2026
*************** gfc_trans_allocate (gfc_code * code, gfc
*** 7538,7544 ****
  
        /* Set the vptr only when no source= is set.  When source= is set, then
  	 the trans_assignment below will set the vptr.  */
!       if (al_vptr != NULL_TREE && (!code->expr3 || code->expr3->mold))
  	{
  	  if (expr3_vptr != NULL_TREE)
  	    /* The vtab is already known, so just assign it.  */
--- 7538,7545 ----
  
        /* Set the vptr only when no source= is set.  When source= is set, then
  	 the trans_assignment below will set the vptr.  */
!       if (al_vptr != NULL_TREE && (!code->expr3 || code->expr3->mold
! 				   || code->expr3->ts.type == BT_CLASS))
  	{
  	  if (expr3_vptr != NULL_TREE)
  	    /* The vtab is already known, so just assign it.  */
diff -Nrcpad gcc-16-20260822/gcc/gimple-fold.cc gcc-16-20260829/gcc/gimple-fold.cc
*** gcc-16-20260822/gcc/gimple-fold.cc	Sat Aug 22 22:32:08 2026
--- gcc-16-20260829/gcc/gimple-fold.cc	Sat Aug 29 22:32:07 2026
*************** partial_load_store_mask_state (gcall *ca
*** 5789,5795 ****
    if (len && poly_int_tree_p (len))
      {
        gcc_assert (TREE_CODE (bias) == INTEGER_CST);
!       wlen = wi::to_poly_widest (len) + wi::to_widest (bias);
  
        if (known_eq (wlen, 0))
  	return MASK_ALL_INACTIVE;
--- 5789,5795 ----
    if (len && poly_int_tree_p (len))
      {
        gcc_assert (TREE_CODE (bias) == INTEGER_CST);
!       wlen = wi::to_poly_widest (len) - wi::to_widest (bias);
  
        if (known_eq (wlen, 0))
  	return MASK_ALL_INACTIVE;
diff -Nrcpad gcc-16-20260822/gcc/multiple_target.cc gcc-16-20260829/gcc/multiple_target.cc
*** gcc-16-20260822/gcc/multiple_target.cc	Sat Aug 22 22:32:09 2026
--- gcc-16-20260829/gcc/multiple_target.cc	Sat Aug 29 22:32:07 2026
*************** create_dispatcher_calls (struct cgraph_n
*** 190,196 ****
  		}
  
  	      symtab_node *source = ref->referring;
! 	      source->create_reference (inode, IPA_REF_ADDR);
  	    }
  	  else if (ref->use == IPA_REF_ALIAS)
  	    {
--- 190,196 ----
  		}
  
  	      symtab_node *source = ref->referring;
! 	      source->create_reference (inode, IPA_REF_ADDR, ref->stmt);
  	    }
  	  else if (ref->use == IPA_REF_ALIAS)
  	    {
diff -Nrcpad gcc-16-20260822/gcc/testsuite/ChangeLog gcc-16-20260829/gcc/testsuite/ChangeLog
*** gcc-16-20260822/gcc/testsuite/ChangeLog	Sat Aug 22 22:32:09 2026
--- gcc-16-20260829/gcc/testsuite/ChangeLog	Sat Aug 29 22:32:08 2026
***************
*** 1,3 ****
--- 1,153 ----
+ 2026-08-28  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-08-28  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/127105
+ 	* gcc.dg/vect/vect-pr127105.c: New testcase.
+ 
+ 2026-08-28  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	Backported from master:
+ 	2026-08-26  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
+ 
+ 	* gcc.dg/vect/pr122797.c: Remove explict "dg-do run".
+ 	* gcc.dg/vect/pr123731.c: Likewise.
+ 
+ 2026-08-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-08-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR tree-optimization/127100
+ 	* gfortran.dg/pr127100.f90: New test.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/120681
+ 	* gcc.target/powerpc/pr120681.c: New test.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/120528
+ 	* gcc.target/powerpc/pr120528.c: New test.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/99293
+ 	* gcc.target/powerpc/pr99293.c: New test.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	PR target/117487
+ 	* gcc.target/powerpc/pr117487.c: New test.
+ 
+ 2026-08-27  Michael Meissner  <meissner@linux.ibm.com>
+ 
+ 	* gcc.target/powerpc/future-3.c: New test.
+ 
+ 2026-08-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-08-24  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	* gcc.dg/builtin-stdc-bit-1.c (main): Fix two pastos.
+ 
+ 2026-08-26  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/opt110.adb: New test.
+ 
+ 2026-08-26  Dipesh Sharma  <Dipesh.Sharma@amd.com>
+ 
+ 	Backported from master:
+ 	2026-08-25  Dipesh Sharma  <Dipesh.Sharma@amd.com>
+ 
+ 	* gcc.target/i386/avx512bmm-check-1.c: New test.
+ 	* gcc.target/i386/avx512bmm-check-2.c: New test.
+ 	* gcc.target/i386/avx512bmm-check-3.c: New test.
+ 
+ 2026-08-26  Alexandre Oliva  <oliva@adacore.com>
+ 
+ 	Backported from master:
+ 	2026-08-26  Alexandre Oliva  <oliva@adacore.com>
+ 
+ 	PR tree-optimization/126650
+ 	* gcc.dg/torture/pr126650.c: Be explicit about endianness
+ 	expectations.
+ 
+ 2026-08-25  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-08-09  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/98573
+ 	* gfortran.dg/allocate_class_5.f90: New test.
+ 
+ 2026-08-25  Josef Melcr  <josef.melcr@suse.com>
+ 
+ 	Backported from master:
+ 	2026-08-25  Josef Melcr  <josef.melcr@suse.com>
+ 
+ 	PR ipa/127023
+ 	* gcc.target/i386/pr127023.c: New test.
+ 
+ 2026-08-24  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-08-22  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/124888
+ 	* g++.dg/modules/typeid-2_a.C: New test.
+ 	* g++.dg/modules/typeid-2_b.C: New test.
+ 
+ 2026-08-24  Jin Ma  <jinma@linux.alibaba.com>
+ 
+ 	Backported from master:
+ 	2026-08-21  Jin Ma  <jinma@linux.alibaba.com>
+ 
+ 	PR target/126873
+ 	* gcc.target/riscv/pr126873.c: New test.
+ 
+ 2026-08-24  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-08-14  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/126426
+ 	* gcc.target/riscv/pr126426.c: New test.
+ 
+ 2026-08-24  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/array43.adb: New test.
+ 
+ 2026-08-24  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-03  Steven G. Kargl  <kargl@gcc.gnu.org>
+ 
+ 	PR fortran/105594
+ 	* gfortran.dg/pr105594.f90: New test.
+ 
+ 2026-08-24  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-02  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/88632
+ 	PR fortran/104630
+ 	* gfortran.dg/submodule_35.f90: New test.
+ 	* gfortran.dg/submodule_35_aux.f90: Submodule and program for
+ 	for the new test.
+ 	Assisted by: Claude Sonnet 4.6
+ 
+ 2026-08-24  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-08-23  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/127004
+ 	* gcc.target/avr/torture/pr127004.c: New test.
+ 
  2026-08-21  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260822/gcc/testsuite/g++.dg/modules/typeid-2_a.C gcc-16-20260829/gcc/testsuite/g++.dg/modules/typeid-2_a.C
*** gcc-16-20260822/gcc/testsuite/g++.dg/modules/typeid-2_a.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/g++.dg/modules/typeid-2_a.C	Sat Aug 29 22:32:09 2026
***************
*** 0 ****
--- 1,12 ----
+ // PR c++/124888
+ // { dg-additional-options -fmodules }
+ 
+ module;
+ #include <typeinfo>
+ export module foo;
+ 
+ export template <class T>
+ const std::type_info &f(T *p)
+ {
+   return typeid (*p);
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/g++.dg/modules/typeid-2_b.C gcc-16-20260829/gcc/testsuite/g++.dg/modules/typeid-2_b.C
*** gcc-16-20260822/gcc/testsuite/g++.dg/modules/typeid-2_b.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/g++.dg/modules/typeid-2_b.C	Sat Aug 29 22:32:09 2026
***************
*** 0 ****
--- 1,12 ----
+ // { dg-additional-options -fmodules }
+ 
+ import foo;
+ 
+ struct A { };
+ struct B { virtual void f() { } };
+ 
+ void g(A* a, B* b)
+ {
+   f (a);
+   f (b);
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.dg/builtin-stdc-bit-1.c gcc-16-20260829/gcc/testsuite/gcc.dg/builtin-stdc-bit-1.c
*** gcc-16-20260822/gcc/testsuite/gcc.dg/builtin-stdc-bit-1.c	Sat Aug 22 22:32:12 2026
--- gcc-16-20260829/gcc/testsuite/gcc.dg/builtin-stdc-bit-1.c	Sat Aug 29 22:32:11 2026
*************** main ()
*** 891,897 ****
        || __builtin_stdc_bit_floor (~(unsigned _BitInt(373)) 0) != ((unsigned _BitInt(373)) 1) << (373 - 1))
      __builtin_abort ();
    if (__builtin_stdc_bit_floor (((unsigned _BitInt(512)) 511) << 405) != (((unsigned _BitInt(512)) 256) << 405)
!       || __builtin_stdc_bit_floor (((unsigned _BitInt(373)) 512) << 242) != (((unsigned _BitInt(512)) 512) << 242))
      __builtin_abort ();
    if (__builtin_stdc_bit_ceil ((unsigned _BitInt(512)) 0) != 1
        || !expr_has_type (__builtin_stdc_bit_ceil ((unsigned _BitInt(512)) 0), unsigned _BitInt(512))
--- 891,897 ----
        || __builtin_stdc_bit_floor (~(unsigned _BitInt(373)) 0) != ((unsigned _BitInt(373)) 1) << (373 - 1))
      __builtin_abort ();
    if (__builtin_stdc_bit_floor (((unsigned _BitInt(512)) 511) << 405) != (((unsigned _BitInt(512)) 256) << 405)
!       || __builtin_stdc_bit_floor (((unsigned _BitInt(373)) 512) << 242) != (((unsigned _BitInt(373)) 512) << 242))
      __builtin_abort ();
    if (__builtin_stdc_bit_ceil ((unsigned _BitInt(512)) 0) != 1
        || !expr_has_type (__builtin_stdc_bit_ceil ((unsigned _BitInt(512)) 0), unsigned _BitInt(512))
*************** main ()
*** 905,911 ****
        || __builtin_stdc_bit_ceil ((~(unsigned _BitInt(373)) 0) >> 1) != ((unsigned _BitInt(373)) 1) << (373 - 1))
      __builtin_abort ();
    if (__builtin_stdc_bit_ceil (((unsigned _BitInt(512)) 512) << 405) != (((unsigned _BitInt(512)) 512) << 405)
!       || __builtin_stdc_bit_ceil (((unsigned _BitInt(373)) 513) << 242) != (((unsigned _BitInt(512)) 1024) << 242))
      __builtin_abort ();
    if (__builtin_stdc_bit_floor ((unsigned _BitInt(__BITINT_MAXWIDTH__)) 0) != 0)
      __builtin_abort ();
--- 905,911 ----
        || __builtin_stdc_bit_ceil ((~(unsigned _BitInt(373)) 0) >> 1) != ((unsigned _BitInt(373)) 1) << (373 - 1))
      __builtin_abort ();
    if (__builtin_stdc_bit_ceil (((unsigned _BitInt(512)) 512) << 405) != (((unsigned _BitInt(512)) 512) << 405)
!       || __builtin_stdc_bit_ceil (((unsigned _BitInt(373)) 513) << 242) != (((unsigned _BitInt(373)) 1024) << 242))
      __builtin_abort ();
    if (__builtin_stdc_bit_floor ((unsigned _BitInt(__BITINT_MAXWIDTH__)) 0) != 0)
      __builtin_abort ();
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.dg/torture/pr126650.c gcc-16-20260829/gcc/testsuite/gcc.dg/torture/pr126650.c
*** gcc-16-20260822/gcc/testsuite/gcc.dg/torture/pr126650.c	Sat Aug 22 22:32:12 2026
--- gcc-16-20260829/gcc/testsuite/gcc.dg/torture/pr126650.c	Sat Aug 29 22:32:11 2026
***************
*** 1,4 ****
! /* { dg-do run } */
  
  #include <stdarg.h>
  #include <stdlib.h>
--- 1,4 ----
! /* { dg-do run { target { le || be } } } */
  
  #include <stdarg.h>
  #include <stdlib.h>
*************** void __attribute__((noipa)) foo (int n,
*** 17,30 ****
  
  int main()
  {
!   struct b {
      int : 7;
      int : 2;
      int : 6;
      int : 3;
      int c : 7;
    };
!   union {
      int d;
      struct b bf;
      char e[4];
--- 17,30 ----
  
  int main()
  {
!   struct __attribute__ ((scalar_storage_order ("little-endian"))) b {
      int : 7;
      int : 2;
      int : 6;
      int : 3;
      int c : 7;
    };
!   union __attribute__ ((scalar_storage_order ("little-endian"))) {
      int d;
      struct b bf;
      char e[4];
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.dg/vect/pr122797.c gcc-16-20260829/gcc/testsuite/gcc.dg/vect/pr122797.c
*** gcc-16-20260822/gcc/testsuite/gcc.dg/vect/pr122797.c	Sat Aug 22 22:32:13 2026
--- gcc-16-20260829/gcc/testsuite/gcc.dg/vect/pr122797.c	Sat Aug 29 22:32:11 2026
***************
*** 1,4 ****
- /* { dg-do run } */
  /* { dg-additional-options "-O3" } */
  
  int src_stride = 0;
--- 1,3 ----
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.dg/vect/pr123731.c gcc-16-20260829/gcc/testsuite/gcc.dg/vect/pr123731.c
*** gcc-16-20260822/gcc/testsuite/gcc.dg/vect/pr123731.c	Sat Aug 22 22:32:13 2026
--- gcc-16-20260829/gcc/testsuite/gcc.dg/vect/pr123731.c	Sat Aug 29 22:32:11 2026
***************
*** 1,5 ****
- /* { dg-do run } */
- 
  typedef unsigned short A __attribute__ ((vector_size (4 * sizeof (short))));
  typedef short B __attribute__ ((vector_size (8 * sizeof (short))));
  typedef unsigned C __attribute__ ((vector_size (4 * sizeof (int))));
--- 1,3 ----
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.dg/vect/vect-pr127105.c gcc-16-20260829/gcc/testsuite/gcc.dg/vect/vect-pr127105.c
*** gcc-16-20260822/gcc/testsuite/gcc.dg/vect/vect-pr127105.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.dg/vect/vect-pr127105.c	Sat Aug 29 22:32:12 2026
***************
*** 0 ****
--- 1,12 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-O3 -fno-tree-pre" } */
+ 
+ int a;
+ char c_0;
+ void main() {
+   int f;
+   for (int d = 0; d < 3; d++) {
+     f = a ? c_0 : 0;
+     c_0 = f;
+   }
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/avr/torture/pr127004.c gcc-16-20260829/gcc/testsuite/gcc.target/avr/torture/pr127004.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/avr/torture/pr127004.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/avr/torture/pr127004.c	Sat Aug 29 22:32:12 2026
***************
*** 0 ****
--- 1,7 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-std=c99" } */
+ 
+ unsigned f (unsigned x)
+ {
+   return (unsigned) (((unsigned long long) x * 0xAAAAAAAB) >> 32) >> 1;
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/avr/torture/pr127098.c gcc-16-20260829/gcc/testsuite/gcc.target/avr/torture/pr127098.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/avr/torture/pr127098.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/avr/torture/pr127098.c	Sat Aug 29 22:32:12 2026
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do run } */
+ 
+ #define NI __attribute((noipa))
+ 
+ typedef char U __attribute__ ((vector_size (16)));
+ 
+ NI void fun (long i, U u)
+ {
+   (void) i;
+   if (u[0] != 1)
+     __builtin_abort ();
+ }
+ 
+ U u = { 1 };
+ 
+ int main (void)
+ {
+   fun (0, u);
+ 
+   return 0;
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/i386/avx512bmm-check-1.c gcc-16-20260829/gcc/testsuite/gcc.target/i386/avx512bmm-check-1.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/i386/avx512bmm-check-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/i386/avx512bmm-check-1.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,6 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -march=znver6" } */
+ 
+ #ifndef __AVX512BMM__
+ # error AVX512BMM should be enabled for target znver6.
+ #endif
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/i386/avx512bmm-check-2.c gcc-16-20260829/gcc/testsuite/gcc.target/i386/avx512bmm-check-2.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/i386/avx512bmm-check-2.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/i386/avx512bmm-check-2.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,20 ----
+ /* { dg-do run } */
+ /* { dg-options "-O2 -march=native" } */
+ 
+ int
+ main ()
+ {
+   if (__builtin_cpu_supports ("avx512bmm"))
+     {
+ #ifndef __AVX512BMM__
+       __builtin_abort ();
+ #endif
+     }
+   else
+     {
+ #ifdef __AVX512BMM__
+       __builtin_abort ();
+ #endif
+     }
+   return 0;
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/i386/avx512bmm-check-3.c gcc-16-20260829/gcc/testsuite/gcc.target/i386/avx512bmm-check-3.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/i386/avx512bmm-check-3.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/i386/avx512bmm-check-3.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,6 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -march=native -mno-avx512bmm" } */
+ 
+ #if defined(__ZNVER6__) && defined(__AVX512BMM__)
+ # error AVX512BMM should be disabled for native detection of target znver6 with -mno-avx512bmm.
+ #endif
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/i386/pr127023.c gcc-16-20260829/gcc/testsuite/gcc.target/i386/pr127023.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/i386/pr127023.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/i386/pr127023.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,16 ----
+ /* PR ipa/127023 */
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -fopenmp" } */
+ /* { dg-require-ifunc "" } */
+ 
+ __attribute__((target_clones("default", "fma4"), noinline))
+ static void e(int f) {
+   if (!f)
+ #pragma omp parallel
+     for (;;)
+       ;
+ }
+ __attribute__((target_clones("default", "fma4")))
+ void g(void) {
+   e(1);
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/future-3.c gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/future-3.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/future-3.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/future-3.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,22 ----
+ /* 32-bit doesn't generate vector pair instructions.  */
+ /* { dg-do compile { target lp64 } } */
+ /* { dg-options "-mdejagnu-cpu=future -O2" } */
+ 
+ /* Test to see that memcpy will use load/store vector pair with
+    -mcpu=future.  */
+ 
+ #ifndef SIZE
+ #define SIZE 4
+ #endif
+ 
+ extern vector double to[SIZE], from[SIZE];
+ 
+ void
+ copy (void)
+ {
+   __builtin_memcpy (to, from, sizeof (to));
+   return;
+ }
+ 
+ /* { dg-final { scan-assembler {\mlxvpx?\M}  } } */
+ /* { dg-final { scan-assembler {\mstxvpx?\M} } } */
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr117487.c gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr117487.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr117487.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr117487.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,67 ----
+ /* { dg-do compile { target lp64 } } */
+ /* { dg-options "-mdejagnu-cpu=power9 -O2" } */
+ /* { dg-require-effective-target powerpc_vsx } */
+ 
+ #include <stdint.h>
+ 
+ /*
+  * PR target/117487
+  *
+  * On power8 with the optimization it generates:
+  *
+  *	xscvdpspn 0,1
+  *	sldi 9,4,32
+  *	mtvsrd 32,9
+  *	xxland 1,0,32
+  *	xscvspdpn 1,1
+  *
+  * I.e., it converts the SFmode to the memory format (instead of the DFmode
+  * that is used within the register), converts the mask so that it is in the
+  * vector register in the upper 32-bits, and does a XXLAND (i.e. there is only
+  * one direct move from GPR to vector register).  Then after doing this, it
+  * converts the upper 32-bits back to DFmode.
+  *
+  * If the XSCVSPDN instruction took the value in the normal 32-bit scalar in a
+  * vector register, we wouldn't have needed the SLDI of the mask.
+  *
+  * On power9/power10/power11 before the fix wa applied, GCC generated:
+  *
+  *	xscvdpspn 0,1
+  *	mfvsrwz 2,0
+  *	and 2,2,4
+  *	mtvsrws 1,2
+  *	xscvspdpn 1,1
+  *	blr
+  *
+  * I.e convert to SFmode representation, move the value to a GPR, do an AND
+  * operation, move the 32-bit value with a splat, and then convert it back to
+  * DFmode format.
+  *
+  * After the patch was applied, it now generates:
+  *
+  *	xscvdpspn 0,1
+  *	mtvsrwz 32,2
+  *	xxland 32,0,32
+  *	xxspltw 1,32,1
+  *	xscvspdpn 1,1
+  *	blr
+  */
+ 
+ union u {
+   float f;
+   uint32_t u32;
+ };
+ 
+ float
+ math_foo (float x, unsigned int mask)
+ {
+   union u arg;
+ 
+   arg.f = x;
+   arg.u32 &= mask;
+   return arg.f;
+ }
+ 
+ /* { dg-final { scan-assembler     {\mxxland\M} } } */
+ /* { dg-final { scan-assembler-not {\mmfvsr}    } } */
+ /* { dg-final { scan-assembler-not {\mand\M}    } } */
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr120528.c gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr120528.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr120528.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr120528.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,91 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target int128 } */
+ /* { dg-require-effective-target lp64 } */
+ /* { dg-require-effective-target power10_ok } */
+ /* { dg-options "-mdejagnu-cpu=power10 -O2" } */
+ 
+ #include <stddef.h>
+ 
+ #ifndef TYPE
+ #define TYPE unsigned long long
+ #endif
+ 
+ void
+ mem_to_vsx (TYPE *p, __uint128_t *q)
+ {
+   /* lxvrdx 0,0,3
+      stxv 0,0(4)  */
+ 
+   __uint128_t x = *p;
+   __asm__ (" # %x0" : "+wa" (x));
+   *q = x;
+ }
+ 
+ void
+ memx_to_vsx (TYPE *p, size_t n, __uint128_t *q)
+ {
+   /* sldi 4,4,3
+      lxvrdx 0,3,4
+      stxv 0,0(4)  */
+ 
+   __uint128_t x = p[n];
+   __asm__ (" # %x0" : "+wa" (x));
+   *q = x;
+ }
+ 
+ void
+ mem3_to_vsx (TYPE *p, __uint128_t *q)
+ {
+   /* addi 2,3,24
+      lxvrdx 0,0,2
+      stxv 0,0(4)  */
+ 
+   __uint128_t x = p[3];
+   __asm__ (" # %x0" : "+wa" (x));
+   *q = x;
+ }
+ 
+ void
+ mem_to_gpr (TYPE *p, __uint128_t *q)
+ {
+   /* ld 2,0(3)
+      li 3,0
+      std 2,0(4)
+      std 3,8(8)  */
+ 
+   __uint128_t x = *p;
+   __asm__ (" # %0" : "+r" (x));
+   *q = x;
+ }
+ 
+ void
+ memx_to_gpr (TYPE *p, size_t n, __uint128_t *q)
+ {
+   /* sldi 4,4,3
+      ldx 2,3,4
+      li 3,0
+      std 2,0(4)
+      std 3,8(8)  */
+ 
+   __uint128_t x = p[n];
+   __asm__ (" # %0" : "+r" (x));
+   *q = x;
+ }
+ 
+ void
+ mem3_to_gpr (TYPE *p, __uint128_t *q)
+ {
+   /* ld 2,24(3)
+      li 3,0
+      std 2,0(4)
+      std 3,8(8)  */
+ 
+   __uint128_t x = p[3];
+   __asm__ (" # %0" : "+r" (x));
+   *q = x;
+ }
+ 
+ /* { dg-final { scan-assembler-times {\maddi\M}   1 } } */
+ /* { dg-final { scan-assembler-times {\mli\M}     3 } } */
+ /* { dg-final { scan-assembler-times {\mlxvrdx\M} 3 } } */
+ /* { dg-final { scan-assembler-times {\mstxv\M}   3 } } */
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr120681.c gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr120681.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr120681.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr120681.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,34 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target powerpc_elfv2 } */
+ /* { dg-require-effective-target powerpc_pcrel } */
+ /* { dg-options "-mdejagnu-cpu=power10 -O2 -mcmodel=large" } */
+ 
+ /* PR target/120681 -- verify that -mcpu=power10 -mcmodel=large uses PC
+    relative addressing instead of using TOC addressing.  */
+ 
+ #ifndef TYPE
+ #define TYPE unsigned long
+ #endif
+ 
+ extern TYPE global_var;
+ 
+ void
+ set_global (TYPE value)
+ {
+   /*
+    * Generate:
+    * pld 9,global_var@got@pcrel
+    * std 3,0(9)
+    *
+    * Not:
+    * addis 9,2,.LC0@toc@ha
+    * ld    9,.LC0@toc@l(9)
+    * std   3,0(9)
+    */
+ 
+   global_var = value;
+ }
+ 
+ /* { dg-final { scan-assembler     {@got@pcrel} } } */
+ /* { dg-final { scan-assembler-not {@toc@ha}    } } */
+ /* { dg-final { scan-assembler-not {@toc@l}     } } */
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr99293.c gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr99293.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/powerpc/pr99293.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/powerpc/pr99293.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,22 ----
+ /* { dg-do compile { target powerpc*-*-* } } */
+ /* { dg-require-effective-target powerpc_vsx_ok } */
+ /* { dg-options "-O2 -mvsx" } */
+ 
+ /* Test for PR 99263, which wants to do:
+ 	__builtin_vec_splats (__builtin_vec_extract (v, n))
+ 
+    where v is a V2DF or V2DI vector and n is either 0 or 1.  Previously the
+    compiler would do a direct move to the GPR registers to select the item and a
+    direct move from the GPR registers to do the splat.  */
+ 
+ vector long long splat_dup_l_0 (vector long long v)
+ {
+   return __builtin_vec_splats (__builtin_vec_extract (v, 0));
+ }
+ 
+ vector long long splat_dup_l_1 (vector long long v)
+ {
+   return __builtin_vec_splats (__builtin_vec_extract (v, 1));
+ }
+ 
+ /* { dg-final { scan-assembler-times "xxpermdi" 2 } } */
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/riscv/pr126426.c gcc-16-20260829/gcc/testsuite/gcc.target/riscv/pr126426.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/riscv/pr126426.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/riscv/pr126426.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,43 ----
+ /* { dg-do run } */
+ /* { dg-additional-options "--std=gnu99 -march=rv64gcb" { target rv64 } } */
+ /* { dg-additional-options "--std=gnu99 -march=rv32gcb" { target rv32 } } */
+ 
+ typedef union {
+   short mv[2];
+   unsigned mv32;
+ } MotionVector;
+ enum { kProjectionMvClamp, kMaxFrameDistance };
+ short kProjectionMvDivisionLookup[] = {0, 6};
+ int SpecGetMvProjectionKernel(int mv, int numerator, int denominator) {
+   int value = mv * numerator * kProjectionMvDivisionLookup[denominator];
+   if (value >= 0)
+     value += 3;
+   value >>= 4;
+   if (value > 4)
+     value = 1;
+   return value;
+ }
+ void SpecGetMvProjectionNoClamp(MotionVector mv, int numerator, int denominator,
+                                 MotionVector *projection_mv) {
+   for (int i = 0; i < 2; ++i)
+     projection_mv->mv[i] =
+         SpecGetMvProjectionKernel(mv.mv[i], numerator, denominator);
+ }
+ int main() {
+   short mvs[5][2] = {{0}};
+   for (int j = 0; j < 5; ++j) {
+     short *mv_value = mvs[j];
+     for (int numerator = -kMaxFrameDistance; numerator; ++numerator)
+       for (int denominator = 0; denominator <= kMaxFrameDistance;
+            ++denominator) {
+         MotionVector mv, spec_projection_mv;
+         mv.mv[0] = mv.mv[1] = mv_value[1];
+         SpecGetMvProjectionNoClamp(mv, numerator, denominator,
+                                    &spec_projection_mv);
+         if (spec_projection_mv.mv32) {
+            __builtin_abort ();
+ 	}
+       }
+   }
+   __builtin_exit (0);
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gcc.target/riscv/pr126873.c gcc-16-20260829/gcc/testsuite/gcc.target/riscv/pr126873.c
*** gcc-16-20260822/gcc/testsuite/gcc.target/riscv/pr126873.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gcc.target/riscv/pr126873.c	Sat Aug 29 22:32:13 2026
***************
*** 0 ****
--- 1,37 ----
+ /* { dg-do run { target rv64 } } */
+ /* { dg-require-effective-target riscv_v } */
+ /* { dg-require-effective-target rvv_zvl128b_ok } */
+ /* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */
+ 
+ typedef unsigned short u16 __attribute__ ((vector_size (4)));
+ 
+ unsigned long long g;
+ 
+ void __attribute__ ((noinline))
+ f1 (unsigned long long a3)
+ {
+   unsigned long long v15
+     = __builtin_bswap64 ((long long) 10398105857157080808ull
+ 			 / (long long) a3);
+   u16 bc13 = (u16) { 29637 };
+   if (0 >= bc13[(unsigned int) v15])
+     __builtin_abort ();
+ }
+ 
+ u16 __attribute__ ((noinline))
+ f2 (u16 in)
+ {
+   in[(unsigned int) g] = 123;
+   return in;
+ }
+ 
+ int
+ main (void)
+ {
+   f1 (17752357569705450221ull);
+   g = 0x0b00000000000000ull;
+   u16 r = f2 ((u16) { 1, 2 });
+   if (r[0] != 123 || r[1] != 2)
+     __builtin_abort ();
+   return 0;
+ }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gfortran.dg/allocate_class_5.f90 gcc-16-20260829/gcc/testsuite/gfortran.dg/allocate_class_5.f90
*** gcc-16-20260822/gcc/testsuite/gfortran.dg/allocate_class_5.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gfortran.dg/allocate_class_5.f90	Sat Aug 29 22:32:14 2026
***************
*** 0 ****
--- 1,134 ----
+ ! { dg-do run }
+ !
+ ! Tests the fix of PR98573. Fixed missing vptrs for class allocations.
+ !
+ ! Contributed by Davis Asanza  <davidhneill@gmail.com>
+ !
+ module counts
+   integer :: integer_count = 0
+   integer :: other_count = 0
+   integer :: alloc_counts = 0
+ end module counts
+ 
+ module foo1
+   use counts
+   type, public:: box
+     class(*), allocatable :: val(:)
+   end type
+ contains
+   subroutine store1(this, val)
+     class(box), intent(out) :: this
+     class(*), intent(in) :: val(:)
+     this%val = val
+   end subroutine store1
+   subroutine store2(this, val)
+     class(box), intent(out) :: this
+     class(*), intent(in) :: val(:)
+     allocate(this%val, source=val)
+   end subroutine store2
+   subroutine vector_type(val)
+     class(*), intent(in) :: val(:)
+     select type (val)
+     type is (integer)
+       integer_count = integer_count + 1
+     class default
+       other_count = other_count + 1
+     end select
+   end subroutine vector_type
+ end module foo1
+ 
+ module foo2
+   use counts
+ contains
+   subroutine store1(arr, val)
+     class(*), allocatable, intent(out) :: arr(:)
+     class(*), intent(in) :: val(:)
+     arr = val
+   end subroutine store1
+   subroutine store2(arr, val)
+     class(*), allocatable, intent(out) :: arr(:)
+     class(*), intent(in) :: val(:)
+     allocate(arr, source=val)
+   end subroutine store2
+ end module foo2
+ 
+ module foo3
+   use counts
+   type, public:: box
+     class(*), allocatable :: val(:)
+   end type
+ contains
+   subroutine store1(this, val)
+     class(box), intent(out) :: this
+     class(*), intent(in) :: val(:)
+     this%val = val
+   end subroutine store1
+   subroutine store2(this, val)
+     class(box), intent(out) :: this
+     class(*), intent(in) :: val(:)
+     allocate(this%val, source=val)
+   end subroutine store2
+   subroutine vector_type(val)
+     class(*), intent(in) :: val(:)
+     select type (val)
+     type is (integer)
+       integer_count = integer_count + 1
+     class default
+       other_count = other_count + 1
+     end select
+   end subroutine vector_type
+ end module foo3
+ 
+ program prog
+   use counts
+   implicit none
+   call bar1  ! Test the original problem
+   call bar2  ! Test comment 1
+   call bar3  ! Test comment 3
+   if (integer_count .ne. 6) stop 1
+   if (other_count .ne. 0) stop 2
+   if (alloc_counts .ne. 2) stop 3
+ contains
+   subroutine bar1
+     use foo1
+     type(box) :: b
+     call store1(b, [1, 2, 3])
+     call vector_type(b%val)  ! OTHER
+     call store2(b, [1, 2, 3])
+     call vector_type(b%val)  ! INTEGER
+   end subroutine bar1
+ 
+   subroutine bar2
+     use foo2
+     class(*), allocatable :: arr(:)
+     call store1(arr, [1, 2, 3])  ! SEGFAULT
+     select type (a => arr)
+       type is (integer)
+         if (all (a .eq. [1, 2, 3])) alloc_counts = alloc_counts + 1
+     end select
+     deallocate (arr)
+     call store2(arr, [1, 2, 3])  ! NO PROBLEM
+     select type (a => arr)
+       type is (integer)
+         if (all (a .eq. [1, 2, 3])) alloc_counts = alloc_counts + 1
+     end select
+   end subroutine bar2
+ 
+   subroutine bar3
+     use foo3
+     type(box) :: b
+     integer, allocatable :: arr1(:)
+     integer, dimension(0) :: arr2
+ 
+     allocate(arr1(0))
+     call store1(b, arr1)
+     call vector_type(b%val)  ! OTHER
+     call store2(b, arr1)
+     call vector_type(b%val)  ! OTHER
+ 
+     call store1(b, arr2)
+     call vector_type(b%val)  ! OTHER
+     call store2(b, arr2)
+     call vector_type(b%val)  ! OTHER
+   end subroutine bar3
+ end program
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gfortran.dg/guality/arg1.f90 gcc-16-20260829/gcc/testsuite/gfortran.dg/guality/arg1.f90
*** gcc-16-20260822/gcc/testsuite/gfortran.dg/guality/arg1.f90	Sat Aug 22 22:32:15 2026
--- gcc-16-20260829/gcc/testsuite/gfortran.dg/guality/arg1.f90	Sat Aug 29 22:32:14 2026
*************** end
*** 8,15 ****
  
  subroutine sub (a, n)
    integer :: a(n), n
    do i = 1, n
      a(i) = i
    end do
!   write (*,*) a	! { dg-final { gdb-test 14 "a(10)" "10" } }
  end subroutine
--- 8,18 ----
  
  subroutine sub (a, n)
    integer :: a(n), n
+   integer, volatile :: v
+   v = 0
    do i = 1, n
      a(i) = i
    end do
!   write (*,*) a
!   v = v + 1	! { dg-final { gdb-test 17 "a(10)" "10" } }
  end subroutine
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gfortran.dg/pr105594.f90 gcc-16-20260829/gcc/testsuite/gfortran.dg/pr105594.f90
*** gcc-16-20260822/gcc/testsuite/gfortran.dg/pr105594.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gfortran.dg/pr105594.f90	Sat Aug 29 22:32:14 2026
***************
*** 0 ****
--- 1,18 ----
+ ! { dg-do compile }
+ ! { dg-options "-Wuse-without-only" }
+ ! PR105594: Spurious warning when compiled with -Wuse-without-only
+ !
+ ! Contributed by Brad Richardson  <everythingfunctional@protonmail.com>
+ !
+ module foo_m
+     interface
+         module subroutine foo
+         end subroutine
+     end interface
+ end module
+ 
+ submodule (foo_m) foo_s
+ contains
+     module procedure foo
+     end procedure
+ end submodule
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gfortran.dg/pr127100.f90 gcc-16-20260829/gcc/testsuite/gfortran.dg/pr127100.f90
*** gcc-16-20260822/gcc/testsuite/gfortran.dg/pr127100.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gfortran.dg/pr127100.f90	Sat Aug 29 22:32:14 2026
***************
*** 0 ****
--- 1,11 ----
+ ! PR tree-optimization/127100
+ ! { dg-do compile { target s390*-*-* } }
+ ! { dg-options "-O2 -march=z13 -fdump-tree-optimized" }
+ ! Verify the test isn't miscompiled into unconditional STOP 1.
+ ! { dg-final { scan-tree-dump "return 0;" "optimized" } }
+ 
+ program main
+   integer(kind=1), dimension(2,2) :: a
+   a = reshape((/ 1_1, 2_1, 3_1, 4_1/), shape(a))
+   if (any(matmul(a,a) /= reshape ( (/ 7, 10, 15, 22 /), shape(a)))) STOP 1
+ end program main
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gfortran.dg/submodule_35.f90 gcc-16-20260829/gcc/testsuite/gfortran.dg/submodule_35.f90
*** gcc-16-20260822/gcc/testsuite/gfortran.dg/submodule_35.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gfortran.dg/submodule_35.f90	Sat Aug 29 22:32:14 2026
***************
*** 0 ****
--- 1,32 ----
+ ! { dg-do run )
+ !
+ ! Test the fix for prs 88632 and 104630, in which the private procedure
+ ! 'my_number' was not visible in the submodule 'decendent'.
+ !
+ ! Contributed by Joerg Stiller <joerg.stiller@tu-dresden.de>
+ !             and Neil Carlson  <neil.n.carlson@gmail.com>
+ !
+ module parent
+   private
+   public :: my_type
+   
+   type my_type
+     integer :: i = 1
+   contains
+     procedure :: my_method
+   end type my_type
+   
+   interface
+     module subroutine my_method(this)
+       class(my_type), intent(inout) :: this
+     end subroutine my_method
+   end interface
+   
+ contains
+   
+   ! common helper function to be used in different submodules
+   integer function my_number()
+     my_number = 42
+   end function my_number
+ 
+ end module parent
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gfortran.dg/submodule_35_aux.f90 gcc-16-20260829/gcc/testsuite/gfortran.dg/submodule_35_aux.f90
*** gcc-16-20260822/gcc/testsuite/gfortran.dg/submodule_35_aux.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gfortran.dg/submodule_35_aux.f90	Sat Aug 29 22:32:14 2026
***************
*** 0 ****
--- 1,19 ----
+ ! { dg-do run }
+ ! { dg-compile-aux-modules "submodule_35.f90" }
+ ! { dg-additional-sources submodule_35.f90 }
+ !
+ submodule(parent) decendent
+ contains
+   module subroutine my_method(this)
+     class(my_type), intent(inout) :: this
+     this%i = my_number()
+   end subroutine my_method
+ end submodule decendent
+ 
+ program main
+   use parent
+   type(my_type) :: my
+   call my % my_method()
+   if (my%i /= 42) stop 1
+ end program main
+ ! { dg-final { cleanup-modules "parent" } }
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gnat.dg/array43.adb gcc-16-20260829/gcc/testsuite/gnat.dg/array43.adb
*** gcc-16-20260822/gcc/testsuite/gnat.dg/array43.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gnat.dg/array43.adb	Sat Aug 29 22:32:15 2026
***************
*** 0 ****
--- 1,19 ----
+ -- { dg-do run }
+ 
+ procedure Array43 is
+ 
+   type Arr is array (Integer range <>) of Integer;
+ 
+   procedure Fill (B : out Arr; N : Integer) is
+   begin
+     B := (1 .. N => 7);
+   end Fill;
+ 
+   V : Arr (5 .. 8) := (others => 0);
+ 
+ begin
+   Fill (V, V'Length);
+   if V /= (V'First .. V'Last => 7) then
+     raise Program_Error;
+   end if;
+ end;
diff -Nrcpad gcc-16-20260822/gcc/testsuite/gnat.dg/opt110.adb gcc-16-20260829/gcc/testsuite/gnat.dg/opt110.adb
*** gcc-16-20260822/gcc/testsuite/gnat.dg/opt110.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/gcc/testsuite/gnat.dg/opt110.adb	Sat Aug 29 22:32:15 2026
***************
*** 0 ****
--- 1,106 ----
+ -- { dg-do run }
+ -- { dg-options "-O" }
+ 
+ procedure Opt110 is
+ 
+   type REAL is new Long_Float;
+ 
+   R : REAL;
+ 
+   N : constant := 3;
+ 
+   C2, S2 : array ( 0..N) of REAL;
+   C, S   : array (-N..0) of REAL;
+ 
+   U, V : REAL;
+ 
+   procedure ADD (C1, S1, C2L, S2L :     REAL;
+                  CO, SO           : out REAL) is
+   begin
+     CO := C1*C2L - S1*S2L;
+     SO := S1*C2L + C1*S2L;
+   end ADD;
+ 
+   procedure TERM (I1, I    : Integer;
+                   DLC, DLS : REAL) is
+   begin
+     ADD (C2(I1), S2(I1), C(I), S(I), U, V);
+     R := R + DLC*U + DLS*V;
+   end TERM;
+ 
+   procedure PERT_1 is
+     COS_M : constant REAL := -0.810937203096633;
+     SIN_M : constant REAL := 0.585133192216790;
+   begin
+     C(-1) := COS_M;
+     S(-1) := -SIN_M;
+     ADD (C(-1), S(-1), C(-1), S(-1), C(-2), S(-2));
+     TERM (1, -1, 0.00,  0.00);
+     TERM (2, -1, 0.25, -0.09);
+   end PERT_1;
+ 
+   procedure PERT_2 is
+     COS_M : constant REAL := -0.977631621135276;
+     SIN_M : constant REAL := 0.210324542924530;
+   begin
+     C(-1) := COS_M;
+     S(-1) := -SIN_M;
+     for I in reverse -(N-1) .. -1 loop
+       ADD (C(I), S(I), C(-1), S(-1), C(I-1), S(I-1));
+     end loop;
+     TERM (1, 0, 2.37, 2793.23);
+   end PERT_2;
+ 
+   procedure PERT_3 is
+     COS_M : constant REAL := 0.682917440967473;
+     SIN_M : constant REAL := 0.730495563862258;
+   begin
+     C(-1) := COS_M;
+     S(-1) := -SIN_M;
+     for I in reverse -2 .. -1 loop
+       ADD (C(I), S(I), C(-1), S(-1), C(I-1), S(I-1));
+     end loop;
+     TERM (1, -3, -0.65, 1.02);
+     TERM (2, -2, -0.05, 0.04);
+     TERM (2, -3, -0.50, 0.45);
+   end PERT_3;
+ 
+   procedure PERT_4 is
+     COS_M : constant REAL := -0.238503621267387;
+     SIN_M : constant REAL := 0.971141607924582;
+   begin
+     C(-1) := COS_M;
+     S(-1) := -SIN_M;
+     for I in reverse -2 .. -1 loop
+       ADD (C(I), S(I), C(-1), S(-1), C(I-1), S(I-1));
+     end loop;
+     TERM (0, -1, -0.05,  1.56);
+     TERM (1, -1, -2.62,  1.40);
+     TERM (1, -2, -0.47, -0.08);
+     TERM (2, -2, -0.73, -0.51);
+     TERM (2, -3, -0.14, -0.10);
+     TERM (3, -3, -0.01,  0.04);
+   end PERT_4;
+ 
+   COS_M : constant REAL := 0.476541619435702;
+   SIN_M : constant REAL := 0.879151912325508;
+ 
+ begin
+   R := 0.0;
+   C(0) := 1.0;
+   S(0) := 0.0;
+   C2(0) := 1.0;
+   S2(0) := 0.0;
+   C2(1) := COS_M;
+   S2(1) := SIN_M;
+   for I in 2 .. N loop
+     ADD (C2(I-1), S2(I-1), C2(1), S2(1), C2(I), S2(I));
+   end loop;
+   PERT_1;
+   PERT_2;
+   PERT_3;
+   PERT_4;
+   if Integer(R) /= 2452 then
+     raise Program_Error;
+   end if;
+ end;
diff -Nrcpad gcc-16-20260822/gcc/tree-dfa.cc gcc-16-20260829/gcc/tree-dfa.cc
*** gcc-16-20260822/gcc/tree-dfa.cc	Sat Aug 22 22:32:16 2026
--- gcc-16-20260829/gcc/tree-dfa.cc	Sat Aug 29 22:32:15 2026
*************** get_ref_base_and_extent (tree exp, poly_
*** 530,559 ****
  		   index.  */
  		seen_variable_array_ref = true;
  
! 		int_range_max vr;
! 		range_query *query;
! 		query = get_range_query (cfun);
  
  		if (TREE_CODE (index) == SSA_NAME
  		    && (low_bound = array_ref_low_bound (exp),
! 			poly_int_tree_p (low_bound))
  		    && (unit_size = array_ref_element_size (exp),
  			TREE_CODE (unit_size) == INTEGER_CST)
  		    && query->range_of_expr (vr, index)
  		    && !vr.varying_p ()
  		    && !vr.undefined_p ())
  		  {
  		    wide_int min = vr.lower_bound ();
  		    wide_int max = vr.upper_bound ();
- 		    poly_offset_int lbound = wi::to_poly_offset (low_bound);
  		    /* Try to constrain maxsize with range information.  */
  		    offset_int omax
  		      = offset_int::from (max, TYPE_SIGN (TREE_TYPE (index)));
  		    if (wi::get_precision (max) <= ADDR_MAX_BITSIZE
! 			&& known_lt (lbound, omax))
  		      {
! 			poly_offset_int rmaxsize;
! 			rmaxsize = (omax - lbound + 1)
  			    * wi::to_offset (unit_size) << LOG2_BITS_PER_UNIT;
  			if (!known_size_p (maxsize)
  			    || known_lt (rmaxsize, maxsize))
--- 530,570 ----
  		   index.  */
  		seen_variable_array_ref = true;
  
! 		/* Try to constrain the access range by using the range of the
! 		   index expression when we know it.  Extra care must be taken
! 		   when the low bound of the array is not zero, because it may
! 		   be very large and the index expression may be unsigned and
! 		   wrap around; in this case, the correct range is that of the
! 		   difference between the index expression and the low bound,
! 		   see get_inner_reference for the model computation.  */
! 		range_query *query = get_range_query (cfun);
! 		range_op_handler minus_op (MINUS_EXPR);
! 		int_range_max vr_idx, vr_lb, vr;
  
  		if (TREE_CODE (index) == SSA_NAME
  		    && (low_bound = array_ref_low_bound (exp),
! 			TREE_CODE (low_bound) == INTEGER_CST)
  		    && (unit_size = array_ref_element_size (exp),
  			TREE_CODE (unit_size) == INTEGER_CST)
  		    && query->range_of_expr (vr, index)
+ 		    && (integer_zerop (low_bound)
+ 			|| ((vr_idx = vr,
+ 			     query->range_of_expr (vr_lb, low_bound))
+ 			    && minus_op.fold_range (vr, TREE_TYPE (index),
+ 						    vr_idx, vr_lb)))
  		    && !vr.varying_p ()
  		    && !vr.undefined_p ())
  		  {
  		    wide_int min = vr.lower_bound ();
  		    wide_int max = vr.upper_bound ();
  		    /* Try to constrain maxsize with range information.  */
  		    offset_int omax
  		      = offset_int::from (max, TYPE_SIGN (TREE_TYPE (index)));
  		    if (wi::get_precision (max) <= ADDR_MAX_BITSIZE
! 			&& omax >= 0)
  		      {
! 			offset_int rmaxsize
! 			  = (omax + 1)
  			    * wi::to_offset (unit_size) << LOG2_BITS_PER_UNIT;
  			if (!known_size_p (maxsize)
  			    || known_lt (rmaxsize, maxsize))
*************** get_ref_base_and_extent (tree exp, poly_
*** 569,579 ****
  		    offset_int omin
  		      = offset_int::from (min, TYPE_SIGN (TREE_TYPE (index)));
  		    if (wi::get_precision (min) <= ADDR_MAX_BITSIZE
! 			&& known_le (lbound, omin))
  		      {
! 			poly_offset_int woffset
! 			  = wi::sext (omin - lbound,
! 				      TYPE_PRECISION (sizetype));
  			woffset *= wi::to_offset (unit_size);
  			woffset <<= LOG2_BITS_PER_UNIT;
  			bit_offset += woffset;
--- 580,589 ----
  		    offset_int omin
  		      = offset_int::from (min, TYPE_SIGN (TREE_TYPE (index)));
  		    if (wi::get_precision (min) <= ADDR_MAX_BITSIZE
! 			&& omin > 0)
  		      {
! 			offset_int woffset
! 			  = wi::sext (omin, TYPE_PRECISION (sizetype));
  			woffset *= wi::to_offset (unit_size);
  			woffset <<= LOG2_BITS_PER_UNIT;
  			bit_offset += woffset;
diff -Nrcpad gcc-16-20260822/gcc/tree-vect-slp.cc gcc-16-20260829/gcc/tree-vect-slp.cc
*** gcc-16-20260822/gcc/tree-vect-slp.cc	Sat Aug 22 22:32:16 2026
--- gcc-16-20260829/gcc/tree-vect-slp.cc	Sat Aug 29 22:32:15 2026
*************** vect_analyze_slp_reduc_chain (loop_vec_i
*** 4266,4274 ****
    if (fail)
      return false;
  
-   /* Remember a stmt with the actual reduction operation.  */
-   stmt_vec_info reduc_scalar_stmt = scalar_stmts[0];
- 
    /* When the SSA def chain through reduc-idx does not form a natural
       reduction chain try to linearize an associative operation manually.  */
    if (scalar_stmts.length () == 1
--- 4266,4271 ----
*************** vect_analyze_slp_reduc_chain (loop_vec_i
*** 4276,4284 ****
        && associative_tree_code ((tree_code)code)
        /* We may not associate if a fold-left reduction is required.  */
        && !needs_fold_left_reduction_p (TREE_TYPE (gimple_get_lhs
! 						    (reduc_scalar_stmt->stmt)),
  				       code))
      {
        auto_vec<chain_op_t> chain;
        auto_vec<std::pair<tree_code, gimple *> > worklist;
        gimple *op_stmt = NULL, *other_op_stmt = NULL;
--- 4273,4283 ----
        && associative_tree_code ((tree_code)code)
        /* We may not associate if a fold-left reduction is required.  */
        && !needs_fold_left_reduction_p (TREE_TYPE (gimple_get_lhs
! 						    (scalar_stmts[0]->stmt)),
  				       code))
      {
+       /* Remember a stmt with the actual reduction operation.  */
+       stmt_vec_info reduc_scalar_stmt = scalar_stmts[0];
        auto_vec<chain_op_t> chain;
        auto_vec<std::pair<tree_code, gimple *> > worklist;
        gimple *op_stmt = NULL, *other_op_stmt = NULL;
diff -Nrcpad gcc-16-20260822/libgcc/config/avr/libf7/ChangeLog gcc-16-20260829/libgcc/config/avr/libf7/ChangeLog
*** gcc-16-20260822/libgcc/config/avr/libf7/ChangeLog	Sat Aug 22 22:32:17 2026
--- gcc-16-20260829/libgcc/config/avr/libf7/ChangeLog	Sat Aug 29 22:32:16 2026
***************
*** 1,3 ****
--- 1,12 ----
+ 2026-08-24  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-08-24  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/127024
+ 	* libf7-asm.sx (to_integer): Don't skip XJMP
+ 	if __AVR_ERRATA_SKIP_JMP_CALL__.
+ 
  2026-08-07  Release Manager
  
  	* GCC 16.2.0 released.
diff -Nrcpad gcc-16-20260822/libgcc/config/avr/libf7/libf7-asm.sx gcc-16-20260829/libgcc/config/avr/libf7/libf7-asm.sx
*** gcc-16-20260822/libgcc/config/avr/libf7/libf7-asm.sx	Sat Aug 22 22:32:17 2026
--- gcc-16-20260829/libgcc/config/avr/libf7/libf7-asm.sx	Sat Aug 29 22:32:16 2026
*************** DEFUN to_integer
*** 602,613 ****
      brmi    .Lsaturate.T    ;   > INTxx_MAX  =>  saturate
  
      brtc 9f                 ;   >= 0         =>  return
      sbrc    Mask,   5
-     .global __negdi2
      XJMP    __negdi2
      sbrc    Mask,   4
-     .global __negsi2
      XJMP    __negsi2
      neg     C6
      neg     C5
      sbci    C6,     0
--- 602,622 ----
      brmi    .Lsaturate.T    ;   > INTxx_MAX  =>  saturate
  
      brtc 9f                 ;   >= 0         =>  return
+ #ifdef __AVR_ERRATA_SKIP_JMP_CALL__
+     ;; Some cores have a problem skipping 2-word instructions.
+     sbrs    Mask,   5
+     rjmp    0f
+     XJMP    __negdi2
+ 0:  sbrs    Mask,   4
+     rjmp    1f
+     XJMP    __negsi2
+ 1:
+ #else
      sbrc    Mask,   5
      XJMP    __negdi2
      sbrc    Mask,   4
      XJMP    __negsi2
+ #endif /* __AVR_ERRATA_SKIP_JMP_CALL__ */
      neg     C6
      neg     C5
      sbci    C6,     0
diff -Nrcpad gcc-16-20260822/libstdc++-v3/ChangeLog gcc-16-20260829/libstdc++-v3/ChangeLog
*** gcc-16-20260822/libstdc++-v3/ChangeLog	Sat Aug 22 22:32:19 2026
--- gcc-16-20260829/libstdc++-v3/ChangeLog	Sat Aug 29 22:32:17 2026
***************
*** 1,3 ****
--- 1,26 ----
+ 2026-08-25  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2026-08-18  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	PR libstdc++/122981
+ 	* include/experimental/bits/simd.h (__int_for_sizeof): Return
+ 	int32_t, int8_t, int16_t, and int64_t, rather than int, signed
+ 	char, short, long, and long long.
+ 	* include/experimental/bits/simd_neon.h (_S_popcount): Cast
+ 	elements to int8_t, int16_t, int32_t, or int64_t, rather than
+ 	signed char, short, int, or long.
+ 
+ 2026-08-25  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-08-24  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/127006
+ 	* include/std/spanstream (basic_ospanstream(span, openmode)):
+ 	Add correct openmode value to parameter.
+ 	* testsuite/27_io/spanstream/127006.cc: New test.
+ 
  2026-08-21  Jonathan Wakely  <jwakely@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260822/libstdc++-v3/include/experimental/bits/simd.h gcc-16-20260829/libstdc++-v3/include/experimental/bits/simd.h
*** gcc-16-20260822/libstdc++-v3/include/experimental/bits/simd.h	Sat Aug 22 22:32:19 2026
--- gcc-16-20260829/libstdc++-v3/include/experimental/bits/simd.h	Sat Aug 29 22:32:18 2026
*************** template <size_t _Bytes>
*** 604,619 ****
    __int_for_sizeof()
    {
      static_assert(_Bytes > 0);
!     if constexpr (_Bytes == sizeof(int))
!       return int();
!     else if constexpr (_Bytes == sizeof(_SChar))
!       return _SChar();
!     else if constexpr (_Bytes == sizeof(short))
!       return short();
!     else if constexpr (_Bytes == sizeof(long))
!       return long();
!     else if constexpr (_Bytes == sizeof(_LLong))
!       return _LLong();
    #ifdef __SIZEOF_INT128__
      else if constexpr (_Bytes == sizeof(__int128))
        return __int128();
--- 604,617 ----
    __int_for_sizeof()
    {
      static_assert(_Bytes > 0);
!     if constexpr (_Bytes == sizeof(int32_t))
!       return int32_t();
!     else if constexpr (_Bytes == sizeof(int8_t))
!       return int8_t();
!     else if constexpr (_Bytes == sizeof(int16_t))
!       return int16_t();
!     else if constexpr (_Bytes == sizeof(int64_t))
!       return int64_t();
    #ifdef __SIZEOF_INT128__
      else if constexpr (_Bytes == sizeof(__int128))
        return __int128();
diff -Nrcpad gcc-16-20260822/libstdc++-v3/include/experimental/bits/simd_neon.h gcc-16-20260829/libstdc++-v3/include/experimental/bits/simd_neon.h
*** gcc-16-20260822/libstdc++-v3/include/experimental/bits/simd_neon.h	Sat Aug 22 22:32:19 2026
--- gcc-16-20260829/libstdc++-v3/include/experimental/bits/simd_neon.h	Sat Aug 29 22:32:18 2026
*************** template <typename _Abi, typename>
*** 480,506 ****
        {
  	if constexpr (sizeof(_Tp) == 1)
  	  {
! 	    const auto __s8 = __vector_bitcast<_SChar>(__k._M_data);
  	    int8x8_t __tmp = __lo64(__s8) + __hi64z(__s8);
  	    return -vpadd_s8(vpadd_s8(vpadd_s8(__tmp, int8x8_t()), int8x8_t()),
  			     int8x8_t())[0];
  	  }
  	else if constexpr (sizeof(_Tp) == 2)
  	  {
! 	    const auto __s16 = __vector_bitcast<short>(__k._M_data);
  	    int16x4_t __tmp = __lo64(__s16) + __hi64z(__s16);
  	    return -vpadd_s16(vpadd_s16(__tmp, int16x4_t()), int16x4_t())[0];
  	  }
  	else if constexpr (sizeof(_Tp) == 4)
  	  {
! 	    const auto __s32 = __vector_bitcast<int>(__k._M_data);
  	    int32x2_t __tmp = __lo64(__s32) + __hi64z(__s32);
  	    return -vpadd_s32(__tmp, int32x2_t())[0];
  	  }
  	else if constexpr (sizeof(_Tp) == 8)
  	  {
  	    static_assert(sizeof(__k) == 16);
! 	    const auto __s64 = __vector_bitcast<long>(__k._M_data);
  	    return -(__s64[0] + __s64[1]);
  	  }
        }
--- 480,506 ----
        {
  	if constexpr (sizeof(_Tp) == 1)
  	  {
! 	    const auto __s8 = __vector_bitcast<int8_t>(__k._M_data);
  	    int8x8_t __tmp = __lo64(__s8) + __hi64z(__s8);
  	    return -vpadd_s8(vpadd_s8(vpadd_s8(__tmp, int8x8_t()), int8x8_t()),
  			     int8x8_t())[0];
  	  }
  	else if constexpr (sizeof(_Tp) == 2)
  	  {
! 	    const auto __s16 = __vector_bitcast<int16_t>(__k._M_data);
  	    int16x4_t __tmp = __lo64(__s16) + __hi64z(__s16);
  	    return -vpadd_s16(vpadd_s16(__tmp, int16x4_t()), int16x4_t())[0];
  	  }
  	else if constexpr (sizeof(_Tp) == 4)
  	  {
! 	    const auto __s32 = __vector_bitcast<int32_t>(__k._M_data);
  	    int32x2_t __tmp = __lo64(__s32) + __hi64z(__s32);
  	    return -vpadd_s32(__tmp, int32x2_t())[0];
  	  }
  	else if constexpr (sizeof(_Tp) == 8)
  	  {
  	    static_assert(sizeof(__k) == 16);
! 	    const auto __s64 = __vector_bitcast<int64_t>(__k._M_data);
  	    return -(__s64[0] + __s64[1]);
  	  }
        }
diff -Nrcpad gcc-16-20260822/libstdc++-v3/include/std/spanstream gcc-16-20260829/libstdc++-v3/include/std/spanstream
*** gcc-16-20260822/libstdc++-v3/include/std/spanstream	Sat Aug 22 22:32:19 2026
--- gcc-16-20260829/libstdc++-v3/include/std/spanstream	Sat Aug 29 22:32:18 2026
*************** template<typename _CharT, typename _Trai
*** 342,348 ****
      basic_ospanstream(std::span<_CharT> __s,
  		      ios_base::openmode __which = ios_base::out)
      : __ostream_type(std::__addressof(_M_sb)),
!       _M_sb(__s, __which | ios_base::in)
      { }
  
      basic_ospanstream(const basic_ospanstream&) = delete;
--- 342,348 ----
      basic_ospanstream(std::span<_CharT> __s,
  		      ios_base::openmode __which = ios_base::out)
      : __ostream_type(std::__addressof(_M_sb)),
!       _M_sb(__s, __which | ios_base::out)
      { }
  
      basic_ospanstream(const basic_ospanstream&) = delete;
diff -Nrcpad gcc-16-20260822/libstdc++-v3/testsuite/27_io/spanstream/127006.cc gcc-16-20260829/libstdc++-v3/testsuite/27_io/spanstream/127006.cc
*** gcc-16-20260822/libstdc++-v3/testsuite/27_io/spanstream/127006.cc	Thu Jan  1 00:00:00 1970
--- gcc-16-20260829/libstdc++-v3/testsuite/27_io/spanstream/127006.cc	Sat Aug 29 22:32:18 2026
***************
*** 0 ****
--- 1,30 ----
+ // { dg-do run { target c++23 } }
+ 
+ #include <spanstream>
+ #include <testsuite_hooks.h>
+ 
+ void
+ test_pr127006_out()
+ {
+   // PR libstdc++/127006
+   char buf[3]{};
+   std::ospanstream s(buf, std::ios::openmode{});
+   VERIFY( s << 'x' );
+   VERIFY( buf[0] == 'x' );
+ }
+ 
+ void
+ test_pr127006_in()
+ {
+   char buf[3]{'x'};
+   std::ispanstream s(buf, std::ios::openmode{});
+   char x;
+   VERIFY( s >> x );
+   VERIFY( x == 'x' );
+ }
+ 
+ int main()
+ {
+   test_pr127006_out();
+   test_pr127006_in();
+ }
