diff -Nrcpad gcc-15-20260814/LAST_UPDATED gcc-15-20260821/LAST_UPDATED
*** gcc-15-20260814/LAST_UPDATED	Fri Aug 14 22:32:22 2026
--- gcc-15-20260821/LAST_UPDATED	Fri Aug 21 22:32:23 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-15 revision 432294890731f1f4921ab10fcc7fec0d52204101
--- 1 ----
! Obtained from git: releases/gcc-15 revision f4f08e3db2d888d25707feb609e4aa5beac46678
diff -Nrcpad gcc-15-20260814/MD5SUMS gcc-15-20260821/MD5SUMS
*** gcc-15-20260814/MD5SUMS	Fri Aug 14 22:32:27 2026
--- gcc-15-20260821/MD5SUMS	Fri Aug 21 22:32:28 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260814.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260821.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
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*************** a798cdca802a57ffa3473ab610b37c86  gcc/fo
*** 6063,6069 ****
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*** 6147,6153 ****
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*************** a4f5f15bbfd3cf3b780e3a8875ebf0df  gcc/fo
*** 6156,6166 ****
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--- 6156,6166 ----
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*************** af420d569eb72f885f4375e275545070  gcc/ta
*** 8450,8456 ****
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*** 53825,53837 ****
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*** 61550,61555 ****
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*************** d399731376ae66ea072cb82782bf310a  gcc/te
*** 61583,61588 ****
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*************** d9ed650f309dc0e24daeb25d90c34fa0  gcc/te
*** 80553,80561 ****
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  daa1cb0a89547fecac9f64b4325b1f0c  gcc/testsuite/gcc.target/i386/pr126429-1.c
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  8951a1fa31f2d45ef9eacfff6a733f77  gcc/testsuite/gcc.target/i386/pr13366.c
  9a752a4b3b77930d91d3c8b0c8897b90  gcc/testsuite/gcc.target/i386/pr13685.c
  31ead0ee84b382ba03e3561931bc6e40  gcc/testsuite/gcc.target/i386/pr14289-1.c
*************** deb12224fed195721b2ddc8b70e46a23  gcc/te
*** 86784,86789 ****
--- 86799,86807 ----
  68e7a002ed920723f1529e366afe30de  gcc/testsuite/gcc.target/powerpc/pr116415.c
  da26cb6383a24e6a94a6c247d777f6b8  gcc/testsuite/gcc.target/powerpc/pr118663.c
  800df636a3d7634e8c0d66c59de11951  gcc/testsuite/gcc.target/powerpc/pr121007.c
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  f0441edf54193f1b965b7d96e3ad8f52  gcc/testsuite/gcc.target/powerpc/pr16155.c
  6f5ca156bb125cbf24502221226bb56e  gcc/testsuite/gcc.target/powerpc/pr16286.c
  198d8a69d2887e8fadcb050d90e21aa6  gcc/testsuite/gcc.target/powerpc/pr16458-1.c
*************** aa358931bdcdffc331e74ec0c69f4a2a  gcc/te
*** 106156,106161 ****
--- 106174,106180 ----
  55dbfeee77bbcb338fb214ad0357a8da  gcc/testsuite/gfortran.dg/pr113503_2.f90
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  b90d3cad8caadc96fae5e6ac9b101803  gcc/testsuite/gfortran.dg/pr114012.f90
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  d832d83a7f0305ed5af20dce6be24b4b  gcc/testsuite/gfortran.dg/pr114304-2.f90
  439f95a81137197be61b0747f76ecd0f  gcc/testsuite/gfortran.dg/pr114304.f90
  e91d746b0b9de2b6ed5529fb46921a0b  gcc/testsuite/gfortran.dg/pr114535d.f90
*************** cbb8fb6fcd7138a90fc489b10fe3c862  gcc/tr
*** 118406,118418 ****
  a58a166bda01c9a970218d3f6c5e330f  gcc/tracer.h
  faec002bae61e7eba3ea45251fbcbc30  gcc/trans-mem.cc
  ffb9a5436754a7e1571b88f970f08891  gcc/trans-mem.h
! b4a6da1471f279353aaca4956c18cdea  gcc/tree-affine.cc
  bcff760f6710b9047412aba72a381983  gcc/tree-affine.h
  527c9fa3845b2653cafc14c109129179  gcc/tree-assume.cc
  918b3dce8ecc8579127255abad77605e  gcc/tree-call-cdce.cc
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  591222e5199894b9b5d23b1822f7e309  gcc/tree-cfg.h
! a48b85120f042a19d52da08d304cc287  gcc/tree-cfgcleanup.cc
  4357345e39068e97ced26f06af8109a6  gcc/tree-cfgcleanup.h
  1718a36253ebbb17fe4570fc768216c9  gcc/tree-chrec.cc
  0e4a484c6387f9be0a506783637432f9  gcc/tree-chrec.h
--- 118425,118437 ----
  a58a166bda01c9a970218d3f6c5e330f  gcc/tracer.h
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  bcff760f6710b9047412aba72a381983  gcc/tree-affine.h
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  591222e5199894b9b5d23b1822f7e309  gcc/tree-cfg.h
! b126682fe531097e50ebc4403051e4eb  gcc/tree-cfgcleanup.cc
  4357345e39068e97ced26f06af8109a6  gcc/tree-cfgcleanup.h
  1718a36253ebbb17fe4570fc768216c9  gcc/tree-chrec.cc
  0e4a484c6387f9be0a506783637432f9  gcc/tree-chrec.h
*************** da72a60de8a6f51a635ead26120d3cc7  gcc/tr
*** 118507,118513 ****
  fcba91260f7125e0b7476810b2adceea  gcc/tree-ssa-pre.cc
  de952b75590b805f05f013f77904e23b  gcc/tree-ssa-propagate.cc
  299c5d8dabcb4a4d30bab51fbedc4e68  gcc/tree-ssa-propagate.h
! 33b23ac0296e477b051caad07dcdfd79  gcc/tree-ssa-reassoc.cc
  258492cd7ef04be49374ea1e670f3b5b  gcc/tree-ssa-reassoc.h
  d34b2911339d018e0b5118b19ae66533  gcc/tree-ssa-sccvn.cc
  4b05103d4706bf37cd0bc9f018b40965  gcc/tree-ssa-sccvn.h
--- 118526,118532 ----
  fcba91260f7125e0b7476810b2adceea  gcc/tree-ssa-pre.cc
  de952b75590b805f05f013f77904e23b  gcc/tree-ssa-propagate.cc
  299c5d8dabcb4a4d30bab51fbedc4e68  gcc/tree-ssa-propagate.h
! b1332383c734f2b857ca312bf0d1d31c  gcc/tree-ssa-reassoc.cc
  258492cd7ef04be49374ea1e670f3b5b  gcc/tree-ssa-reassoc.h
  d34b2911339d018e0b5118b19ae66533  gcc/tree-ssa-sccvn.cc
  4b05103d4706bf37cd0bc9f018b40965  gcc/tree-ssa-sccvn.h
*************** af4c63760c432f66b1c6c8e7e7666699  gcc/tr
*** 118542,118553 ****
  cac3afe79bbadb8c304cebff78dbb3df  gcc/tree-tailcall.cc
  61a9b445a765d6b6d497bc7273d05f64  gcc/tree-vect-data-refs.cc
  cc4b6ecb376a4980bfd08a185c104993  gcc/tree-vect-generic.cc
! cc0bdf3f684b251509b8552d2d8549a3  gcc/tree-vect-loop-manip.cc
  50b45429288c6e81f0bead093f403d8f  gcc/tree-vect-loop.cc
  294fdaba99fd4fb48e7317235676a90b  gcc/tree-vect-patterns.cc
  416ed4e13d1732162428324c31e142e5  gcc/tree-vect-slp-patterns.cc
  c417ef312ca64d3d6d752dc4dfbbc195  gcc/tree-vect-slp.cc
! c391a866336d7eb20bb88915dfda5f2b  gcc/tree-vect-stmts.cc
  c8efeee600d612c4bae8dda4bd45ee54  gcc/tree-vector-builder.cc
  258611ff1e83cc7680e8c9f033499665  gcc/tree-vector-builder.h
  6a5457c324d4279acbd82f147f1dd823  gcc/tree-vectorizer.cc
--- 118561,118572 ----
  cac3afe79bbadb8c304cebff78dbb3df  gcc/tree-tailcall.cc
  61a9b445a765d6b6d497bc7273d05f64  gcc/tree-vect-data-refs.cc
  cc4b6ecb376a4980bfd08a185c104993  gcc/tree-vect-generic.cc
! 18d87416e83bfb992b5bb3276fad69f0  gcc/tree-vect-loop-manip.cc
  50b45429288c6e81f0bead093f403d8f  gcc/tree-vect-loop.cc
  294fdaba99fd4fb48e7317235676a90b  gcc/tree-vect-patterns.cc
  416ed4e13d1732162428324c31e142e5  gcc/tree-vect-slp-patterns.cc
  c417ef312ca64d3d6d752dc4dfbbc195  gcc/tree-vect-slp.cc
! 16b9e683cc8d69d6b9c8507adeefa5cd  gcc/tree-vect-stmts.cc
  c8efeee600d612c4bae8dda4bd45ee54  gcc/tree-vector-builder.cc
  258611ff1e83cc7680e8c9f033499665  gcc/tree-vector-builder.h
  6a5457c324d4279acbd82f147f1dd823  gcc/tree-vectorizer.cc
*************** d680e7307fb59fe24f8431e179191f16  libssp
*** 132592,132598 ****
  534c3fb4a88e5c1f70db35c12b7742c3  libssp/vsnprintf-chk.c
  34daeb04a522ee796098df4446d6ce61  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! 866c7c3fd9335fd8d3369728cb03e560  libstdc++-v3/ChangeLog
  7aa6c40440a44fcf5ec94c066160c2f8  libstdc++-v3/ChangeLog-1998
  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
--- 132611,132617 ----
  534c3fb4a88e5c1f70db35c12b7742c3  libssp/vsnprintf-chk.c
  34daeb04a522ee796098df4446d6ce61  libssp/vsprintf-chk.c
  9e2de2e1f20ab0ffa2201164de02824f  libstdc++-v3/.editorconfig
! 294746610f0619526f3c4f536c68bc6f  libstdc++-v3/ChangeLog
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  7aff86600b6a1ed3fa87305075a92db0  libstdc++-v3/ChangeLog-1999
  a6f28e8fc9bb07696a9e068b439a3a87  libstdc++-v3/ChangeLog-2000
*************** a94321c8d0dbbc71741ebf0f1cc9828c  libstd
*** 132623,132629 ****
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  13f29ef95664bfe876c83f7743ca504d  libstdc++-v3/aclocal.m4
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  9e25b4e524e0d639f272a9e96bab0ce3  libstdc++-v3/config/abi/compatibility.h
--- 132642,132648 ----
  b569b721263ae74c6a8e285903fb9906  libstdc++-v3/Makefile.am
  5ae0a394d413d225772c3b38a114cce2  libstdc++-v3/Makefile.in
  f372af73db4ac0ad88e43199e1f29e08  libstdc++-v3/README
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  9e25b4e524e0d639f272a9e96bab0ce3  libstdc++-v3/config/abi/compatibility.h
*************** ed199f6700a016816d625b286bf25ead  libstd
*** 132817,132823 ****
  8913cf14e458f9cfae745a0d939c97e4  libstdc++-v3/config/os/vxworks/ctype_configure_char.cc
  e29a526ec89ed09bf39b0aa4fd4c5d79  libstdc++-v3/config/os/vxworks/ctype_inline.h
  788b66dfe66c25c24ff60bf253c9c7ff  libstdc++-v3/config/os/vxworks/os_defines.h
! 09c8e0b714892f9ca47efdaabf583f94  libstdc++-v3/configure
  cea931b634158b7ec3ed389b8b5d2de6  libstdc++-v3/configure.ac
  546d8799acc0db2a2a28b658d5665dc3  libstdc++-v3/configure.host
  450cc52f6f6f0abf59940662504c450e  libstdc++-v3/crossconfig.m4
--- 132836,132842 ----
  8913cf14e458f9cfae745a0d939c97e4  libstdc++-v3/config/os/vxworks/ctype_configure_char.cc
  e29a526ec89ed09bf39b0aa4fd4c5d79  libstdc++-v3/config/os/vxworks/ctype_inline.h
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*************** f4af31191dea172207576960ad71d42d  libstd
*** 134007,134013 ****
  ba52fc2e0904a31a08183de15bd8c424  libstdc++-v3/include/std/memory
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  96d4004072aee0df9b1cac29de7649c2  libstdc++-v3/include/std/mutex
! ef0d0725f5b70a4c1b5b62b84b2b63f7  libstdc++-v3/include/std/numbers
  dc13616d50b61cc61eb87d25bacd6a19  libstdc++-v3/include/std/numeric
  79b194dcc53ff3f04fcf800d0fc26cfa  libstdc++-v3/include/std/optional
  e03c583ee7c5891df1c7b190275435c9  libstdc++-v3/include/std/ostream
--- 134026,134032 ----
  ba52fc2e0904a31a08183de15bd8c424  libstdc++-v3/include/std/memory
  9e86c11ff29d60fddf403674e9182b36  libstdc++-v3/include/std/memory_resource
  96d4004072aee0df9b1cac29de7649c2  libstdc++-v3/include/std/mutex
! adf686575c2a77b7d3aedb79977c6aaf  libstdc++-v3/include/std/numbers
  dc13616d50b61cc61eb87d25bacd6a19  libstdc++-v3/include/std/numeric
  79b194dcc53ff3f04fcf800d0fc26cfa  libstdc++-v3/include/std/optional
  e03c583ee7c5891df1c7b190275435c9  libstdc++-v3/include/std/ostream
diff -Nrcpad gcc-15-20260814/gcc/ChangeLog gcc-15-20260821/gcc/ChangeLog
*** gcc-15-20260814/gcc/ChangeLog	Fri Aug 14 22:32:05 2026
--- gcc-15-20260821/gcc/ChangeLog	Fri Aug 21 22:32:06 2026
***************
*** 1,3 ****
--- 1,139 ----
+ 2026-08-20  Hongyu Wang  <hongyu.wang@intel.com>
+ 
+ 	Backported from master:
+ 	2026-08-12  Hongyu Wang  <hongyu.wang@intel.com>
+ 
+ 	PR target/126787
+ 	* config/i386/sse.md (*fma_fmadd_<mode>): Use the "jm" to replace
+ 	"m" constraint and set addr attribute to "gpr16" for vex only
+ 	alternatives.
+ 	(*fma_fmsub_<mode>): Likewise.
+ 	(*fma_fnmadd_<mode>): Likewise.
+ 	(*fma_fnmsub_<mode>): Likewise.
+ 	(*fma_fmaddsub_<mode>): Likewise.
+ 	(*fma_fmsubadd_<mode>): Likewise.
+ 	(xop_p<macs><ssemodesuffix><ssemodesuffix>): Likewise.
+ 	(xop_p<macs>dql): Likewise.
+ 	(xop_p<macs>dqh): Likewise.
+ 	(xop_p<macs>wd): Likewise.
+ 	(xop_p<madcs>wd): Likewise.
+ 	(xop_pcmov_<mode><avxsizesuffix>): Likewise.
+ 	(xop_phadd<u>bw): Likewise.
+ 	(xop_phadd<u>bd): Likewise.
+ 	(xop_phadd<u>bq): Likewise.
+ 	(xop_phadd<u>wd): Likewise.
+ 	(xop_phadd<u>wq): Likewise.
+ 	(xop_phadd<u>dq): Likewise.
+ 	(xop_phsubbw): Likewise.
+ 	(xop_phsubwd): Likewise.
+ 	(xop_phsubdq): Likewise.
+ 	(xop_pperm): Likewise.
+ 	(xop_pperm_pack_v2di_v4si): Likewise.
+ 	(xop_pperm_pack_v4si_v8hi): Likewise.
+ 	(xop_pperm_pack_v8hi_v16qi): Likewise.
+ 	(xop_rotl<mode>3): Likewise.
+ 	(xop_rotr<mode>3): Likewise.
+ 	(xop_vrotl<mode>3): Likewise.
+ 	(xop_sha<mode>3): Likewise.
+ 	(xop_shl<mode>3): Likewise.
+ 	(xop_frcz<mode>2): Likewise.
+ 	(*xop_vmfrcz<mode>2): Likewise.
+ 	(xop_maskcmp<mode>3): Likewise.
+ 	(xop_maskcmp_uns<mode>3): Likewise.
+ 	(xop_maskcmp_uns2<mode>3): Likewise.
+ 	(xop_pcom_tf<mode>3): Likewise.
+ 	(xop_vpermil2<mode>3): Likewise.
+ 
+ 2026-08-20  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-08-10  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	PR target/126513
+ 	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Allocate reg
+ 	if target is null or const0_rtx.
+ 	* config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin): Add
+ 	error handling for c1, c2 and c3 described in this commit.
+ 
+ 2026-08-19  Alice Carlotti  <alice.carlotti@arm.com>
+ 
+ 	PR target/124629
+ 	* config/aarch64/driver-aarch64.cc (AARCH64_ARCH):
+ 	Don't skip first character of #ARCH_IDENT.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-08-05  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/126650
+ 	* tree-affine.cc (get_inner_reference_aff): Fixup rounding
+ 	of size.
+ 
+ 2026-08-19  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2026-07-28  H.J. Lu  <hjl.tools@gmail.com>
+ 		    Richard Biener   <rguenther@suse.de>
+ 
+ 	PR middle-end/126410
+ 	* tree-vect-stmts.cc (vectorizable_store): Only commit to
+ 	recorded base alignment when transforming.
+ 	(vectorizable_load): Likewise.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-06-15  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/125786
+ 	* tree-ssa-reassoc.cc (optimize_vec_cond_expr): Create a new
+ 	stmt instead of rewriting an existing possibly multi-use one.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-06-02  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/125545
+ 	* tree-ssa-reassoc.cc (insert_stmt_after): Allow asm goto
+ 	with a single successor.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-06-03  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/125477
+ 	* tree-vect-loop-manip.cc (vect_loop_versioning): Verify we
+ 	can duplicate an outer loop before considering to version it.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-05-04  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/125156
+ 	* tree-cfgcleanup.cc (cleanup_control_expr_graph): Clear
+ 	EDGE_TRUE_VALUE and EDGE_FALSE_VALUE edge flags only.
+ 
+ 2026-08-19  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	Backported from master:
+ 	2026-06-26  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	PR target/125949
+ 	* config/i386/i386.md ("isa"): Add avxvnniint8.
+ 	("enabled"): Adjust for avxvnniint8.
+ 	* config/i386/sse.md (vpdp<vpdotprodtype>_<mode>): Adjust for
+ 	AVXVNNIINT8.
+ 
+ 2026-08-14  Tamar Christina  <tamar.christina@arm.com>
+ 
+ 	* config/aarch64/aarch64-cores.def (armagicpu): New.
+ 	* config/aarch64/aarch64-tune.md: Renegerate
+ 	* doc/invoke.texi: Document it.
+ 
  2026-08-13  Uros Bizjak  <ubizjak@gmail.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260814/gcc/DATESTAMP gcc-15-20260821/gcc/DATESTAMP
*** gcc-15-20260814/gcc/DATESTAMP	Fri Aug 14 22:32:05 2026
--- gcc-15-20260821/gcc/DATESTAMP	Fri Aug 21 22:32:06 2026
***************
*** 1 ****
! 20260814
--- 1 ----
! 20260821
diff -Nrcpad gcc-15-20260814/gcc/config/aarch64/driver-aarch64.cc gcc-15-20260821/gcc/config/aarch64/driver-aarch64.cc
*** gcc-15-20260814/gcc/config/aarch64/driver-aarch64.cc	Fri Aug 14 22:32:06 2026
--- gcc-15-20260821/gcc/config/aarch64/driver-aarch64.cc	Fri Aug 21 22:32:07 2026
*************** struct aarch64_arch_driver_info
*** 79,87 ****
    aarch64_feature_flags flags;
  };
  
- /* Skip the leading "V" in the architecture name.  */
  #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
!   { #ARCH_IDENT + 1, NAME, feature_deps::ARCH_IDENT ().enable },
  
  static CONSTEXPR const aarch64_arch_driver_info aarch64_arches[] =
  {
--- 79,86 ----
    aarch64_feature_flags flags;
  };
  
  #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
!   { #ARCH_IDENT, NAME, feature_deps::ARCH_IDENT ().enable },
  
  static CONSTEXPR const aarch64_arch_driver_info aarch64_arches[] =
  {
diff -Nrcpad gcc-15-20260814/gcc/config/i386/i386.md gcc-15-20260821/gcc/config/i386/i386.md
*** gcc-15-20260814/gcc/config/i386/i386.md	Fri Aug 14 22:32:07 2026
--- gcc-15-20260821/gcc/config/i386/i386.md	Fri Aug 21 22:32:07 2026
***************
*** 582,590 ****
  		    avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,avx512f_512,
  		    noavx512f,avx512bw,avx512bw_512,noavx512bw,avx512dq,
  		    noavx512dq,fma_or_avx512vl,avx512vl,noavx512vl,avxvnni,
! 		    avx512vnnivl,avx512fp16,avxifma,avx512ifmavl,avxneconvert,
! 		    avx512bf16vl,vpclmulqdqvl,avx_noavx512f,avx_noavx512vl,
! 		    vaes_avx512vl,noapx_nf,avx10_2"
    (const_string "base"))
  
  ;; The (bounding maximum) length of an instruction immediate.
--- 582,590 ----
  		    avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,avx512f_512,
  		    noavx512f,avx512bw,avx512bw_512,noavx512bw,avx512dq,
  		    noavx512dq,fma_or_avx512vl,avx512vl,noavx512vl,avxvnni,
! 		    avxvnniint8,avx512vnnivl,avx512fp16,avxifma,avx512ifmavl,
! 		    avxneconvert,avx512bf16vl,vpclmulqdqvl,avx_noavx512f,
! 		    avx_noavx512vl,vaes_avx512vl,noapx_nf,avx10_2"
    (const_string "base"))
  
  ;; The (bounding maximum) length of an instruction immediate.
***************
*** 966,971 ****
--- 966,972 ----
  	 (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
  	 (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
  	 (eq_attr "isa" "avxvnni") (symbol_ref "TARGET_AVXVNNI")
+ 	 (eq_attr "isa" "avxvnniint8") (symbol_ref "TARGET_AVXVNNIINT8")
  	 (eq_attr "isa" "avx512vnnivl")
  	   (symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL")
  	 (eq_attr "isa" "avx512fp16")
diff -Nrcpad gcc-15-20260814/gcc/config/i386/sse.md gcc-15-20260821/gcc/config/i386/sse.md
*** gcc-15-20260814/gcc/config/i386/sse.md	Fri Aug 14 22:32:07 2026
--- gcc-15-20260821/gcc/config/i386/sse.md	Fri Aug 21 22:32:07 2026
***************
*** 5947,5954 ****
    [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
  	(fma:FMAMODE
  	  (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x")
! 	  (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,m")
! 	  (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xm,x")))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
--- 5947,5954 ----
    [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
  	(fma:FMAMODE
  	  (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x")
! 	  (match_operand:FMAMODE 2 "nonimmediate_operand" "vm,v,vm,x,jm")
! 	  (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xjm,x")))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
***************
*** 5958,5963 ****
--- 5958,5964 ----
     vfmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "fma,fma,fma,fma4,fma4")
     (set_attr "type" "ssemuladd")
+    (set_attr "addr" "*,*,*,gpr16,gpr16")
     (set_attr "mode" "<MODE>")])
  
  ;; Suppose AVX-512F as baseline
***************
*** 6045,6053 ****
    [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
  	(fma:FMAMODE
  	  (match_operand:FMAMODE   1 "nonimmediate_operand" "%0,0,v,x,x")
! 	  (match_operand:FMAMODE   2 "nonimmediate_operand" "vm,v,vm,x,m")
  	  (neg:FMAMODE
! 	    (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xm,x"))))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
--- 6046,6054 ----
    [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x")
  	(fma:FMAMODE
  	  (match_operand:FMAMODE   1 "nonimmediate_operand" "%0,0,v,x,x")
! 	  (match_operand:FMAMODE   2 "nonimmediate_operand" "vm,v,vm,x,jm")
  	  (neg:FMAMODE
! 	    (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xjm,x"))))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfmsub132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
***************
*** 6057,6062 ****
--- 6058,6064 ----
     vfmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "fma,fma,fma,fma4,fma4")
     (set_attr "type" "ssemuladd")
+    (set_attr "addr" "*,*,*,gpr16,gpr16")
     (set_attr "mode" "<MODE>")])
  
  (define_expand "<avx512>_fmsub_<mode>_maskz<round_expand_name>"
***************
*** 6152,6159 ****
  	(fma:FMAMODE
  	  (neg:FMAMODE
  	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x"))
! 	  (match_operand:FMAMODE   2 "nonimmediate_operand" "vm,v,vm,x,m")
! 	  (match_operand:FMAMODE   3 "nonimmediate_operand" "v,vm,0,xm,x")))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
--- 6154,6161 ----
  	(fma:FMAMODE
  	  (neg:FMAMODE
  	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x"))
! 	  (match_operand:FMAMODE   2 "nonimmediate_operand" "vm,v,vm,x,jm")
! 	  (match_operand:FMAMODE   3 "nonimmediate_operand" "v,vm,0,xjm,x")))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfnmadd132<ssemodesuffix>\t{%2, %3, %0|%0, %3, %2}
***************
*** 6163,6168 ****
--- 6165,6171 ----
     vfnmadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "fma,fma,fma,fma4,fma4")
     (set_attr "type" "ssemuladd")
+    (set_attr "addr" "*,*,*,gpr16,gpr16")
     (set_attr "mode" "<MODE>")])
  
  (define_expand "<avx512>_fnmadd_<mode>_maskz<round_expand_name>"
***************
*** 6258,6266 ****
  	(fma:FMAMODE
  	  (neg:FMAMODE
  	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x"))
! 	  (match_operand:FMAMODE   2 "nonimmediate_operand" "vm,v,vm,x,m")
  	  (neg:FMAMODE
! 	    (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xm,x"))))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
--- 6261,6269 ----
  	(fma:FMAMODE
  	  (neg:FMAMODE
  	    (match_operand:FMAMODE 1 "nonimmediate_operand" "%0,0,v,x,x"))
! 	  (match_operand:FMAMODE   2 "nonimmediate_operand" "vm,v,vm,x,jm")
  	  (neg:FMAMODE
! 	    (match_operand:FMAMODE 3 "nonimmediate_operand" "v,vm,0,xjm,x"))))]
    "TARGET_FMA || TARGET_FMA4"
    "@
     vfnmsub132<ssemodesuffix>\t{<round_sd_mask_op4>%2, %3, %0<sd_mask_op4>|%0<sd_mask_op4>, %3, %2<round_sd_mask_op4>}
***************
*** 6270,6275 ****
--- 6273,6279 ----
     vfnmsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "fma,fma,fma,fma4,fma4")
     (set_attr "type" "ssemuladd")
+    (set_attr "addr" "*,*,*,gpr16,gpr16")
     (set_attr "mode" "<MODE>")])
  
  (define_expand "<avx512>_fnmsub_<mode>_maskz<round_expand_name>"
***************
*** 6435,6442 ****
    [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x")
  	(unspec:VF_128_256
  	  [(match_operand:VF_128_256 1 "nonimmediate_operand" "%0,0,v,x,x")
! 	   (match_operand:VF_128_256 2 "nonimmediate_operand" "vm,v,vm,x,m")
! 	   (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xm,x")]
  	  UNSPEC_FMADDSUB))]
    "TARGET_FMA || TARGET_FMA4"
    "@
--- 6439,6446 ----
    [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x")
  	(unspec:VF_128_256
  	  [(match_operand:VF_128_256 1 "nonimmediate_operand" "%0,0,v,x,x")
! 	   (match_operand:VF_128_256 2 "nonimmediate_operand" "vm,v,vm,x,jm")
! 	   (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xjm,x")]
  	  UNSPEC_FMADDSUB))]
    "TARGET_FMA || TARGET_FMA4"
    "@
***************
*** 6447,6452 ****
--- 6451,6457 ----
     vfmaddsub<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "fma,fma,fma,fma4,fma4")
     (set_attr "type" "ssemuladd")
+    (set_attr "addr" "*,*,*,gpr16,gpr16")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "<sd_mask_codefor>fma_fmaddsub_<mode><sd_maskz_name><round_name>"
***************
*** 6503,6511 ****
    [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x")
  	(unspec:VF_128_256
  	  [(match_operand:VF_128_256   1 "nonimmediate_operand" "%0,0,v,x,x")
! 	   (match_operand:VF_128_256   2 "nonimmediate_operand" "vm,v,vm,x,m")
  	   (neg:VF_128_256
! 	     (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xm,x"))]
  	  UNSPEC_FMADDSUB))]
    "TARGET_FMA || TARGET_FMA4"
    "@
--- 6508,6516 ----
    [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x")
  	(unspec:VF_128_256
  	  [(match_operand:VF_128_256   1 "nonimmediate_operand" "%0,0,v,x,x")
! 	   (match_operand:VF_128_256   2 "nonimmediate_operand" "vm,v,vm,x,jm")
  	   (neg:VF_128_256
! 	     (match_operand:VF_128_256 3 "nonimmediate_operand" "v,vm,0,xjm,x"))]
  	  UNSPEC_FMADDSUB))]
    "TARGET_FMA || TARGET_FMA4"
    "@
***************
*** 6516,6521 ****
--- 6521,6527 ----
     vfmsubadd<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "fma,fma,fma,fma4,fma4")
     (set_attr "type" "ssemuladd")
+    (set_attr "addr" "*,*,*,gpr16,gpr16")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "<sd_mask_codefor>fma_fmsubadd_<mode><sd_maskz_name><round_name>"
***************
*** 26509,26520 ****
  	(xop_plus:VI24_128
  	 (mult:VI24_128
  	  (match_operand:VI24_128 1 "nonimmediate_operand" "%x")
! 	  (match_operand:VI24_128 2 "nonimmediate_operand" "xm"))
  	 (match_operand:VI24_128 3 "register_operand" "x")))]
    "TARGET_XOP"
    "vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_p<macs>dql"
--- 26515,26527 ----
  	(xop_plus:VI24_128
  	 (mult:VI24_128
  	  (match_operand:VI24_128 1 "nonimmediate_operand" "%x")
! 	  (match_operand:VI24_128 2 "nonimmediate_operand" "xjm"))
  	 (match_operand:VI24_128 3 "register_operand" "x")))]
    "TARGET_XOP"
    "vp<macs><ssemodesuffix><ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_p<macs>dql"
***************
*** 26527,26539 ****
  	    (parallel [(const_int 0) (const_int 2)])))
  	  (sign_extend:V2DI
  	   (vec_select:V2SI
! 	    (match_operand:V4SI 2 "nonimmediate_operand" "xm")
  	    (parallel [(const_int 0) (const_int 2)]))))
  	 (match_operand:V2DI 3 "register_operand" "x")))]
    "TARGET_XOP"
    "vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_p<macs>dqh"
--- 26534,26547 ----
  	    (parallel [(const_int 0) (const_int 2)])))
  	  (sign_extend:V2DI
  	   (vec_select:V2SI
! 	    (match_operand:V4SI 2 "nonimmediate_operand" "xjm")
  	    (parallel [(const_int 0) (const_int 2)]))))
  	 (match_operand:V2DI 3 "register_operand" "x")))]
    "TARGET_XOP"
    "vp<macs>dql\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_p<macs>dqh"
***************
*** 26546,26558 ****
  	    (parallel [(const_int 1) (const_int 3)])))
  	  (sign_extend:V2DI
  	   (vec_select:V2SI
! 	    (match_operand:V4SI 2 "nonimmediate_operand" "xm")
  	    (parallel [(const_int 1) (const_int 3)]))))
  	 (match_operand:V2DI 3 "register_operand" "x")))]
    "TARGET_XOP"
    "vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
     (set_attr "mode" "TI")])
  
  ;; XOP parallel integer multiply/add instructions for the intrinisics
--- 26554,26567 ----
  	    (parallel [(const_int 1) (const_int 3)])))
  	  (sign_extend:V2DI
  	   (vec_select:V2SI
! 	    (match_operand:V4SI 2 "nonimmediate_operand" "xjm")
  	    (parallel [(const_int 1) (const_int 3)]))))
  	 (match_operand:V2DI 3 "register_operand" "x")))]
    "TARGET_XOP"
    "vp<macs>dqh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; XOP parallel integer multiply/add instructions for the intrinisics
***************
*** 26567,26573 ****
  		       (const_int 5) (const_int 7)])))
  	  (sign_extend:V4SI
  	   (vec_select:V4HI
! 	    (match_operand:V8HI 2 "nonimmediate_operand" "xm")
  	    (parallel [(const_int 1) (const_int 3)
  		       (const_int 5) (const_int 7)]))))
  	 (match_operand:V4SI 3 "register_operand" "x")))]
--- 26576,26582 ----
  		       (const_int 5) (const_int 7)])))
  	  (sign_extend:V4SI
  	   (vec_select:V4HI
! 	    (match_operand:V8HI 2 "nonimmediate_operand" "xjm")
  	    (parallel [(const_int 1) (const_int 3)
  		       (const_int 5) (const_int 7)]))))
  	 (match_operand:V4SI 3 "register_operand" "x")))]
***************
*** 26575,26580 ****
--- 26584,26590 ----
    "vp<macs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_p<madcs>wd"
***************
*** 26589,26595 ****
  			(const_int 4) (const_int 6)])))
  	   (sign_extend:V4SI
  	    (vec_select:V4HI
! 	     (match_operand:V8HI 2 "nonimmediate_operand" "xm")
  	     (parallel [(const_int 0) (const_int 2)
  			(const_int 4) (const_int 6)]))))
  	  (mult:V4SI
--- 26599,26605 ----
  			(const_int 4) (const_int 6)])))
  	   (sign_extend:V4SI
  	    (vec_select:V4HI
! 	     (match_operand:V8HI 2 "nonimmediate_operand" "xjm")
  	     (parallel [(const_int 0) (const_int 2)
  			(const_int 4) (const_int 6)]))))
  	  (mult:V4SI
***************
*** 26608,26625 ****
    "vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
     (set_attr "mode" "TI")])
  
  ;; XOP parallel XMM conditional moves
  (define_insn "xop_pcmov_<mode><avxsizesuffix>"
    [(set (match_operand:V_128_256 0 "register_operand" "=x,x")
  	(if_then_else:V_128_256
! 	  (match_operand:V_128_256 3 "nonimmediate_operand" "x,m")
  	  (match_operand:V_128_256 1 "register_operand" "x,x")
! 	  (match_operand:V_128_256 2 "nonimmediate_operand" "xm,x")))]
    "TARGET_XOP"
    "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "<sseinsnmode>")])
  
  ;; Recognize XOP's vpcmov from canonical (xor (and (xor t f) c) f)
--- 26618,26637 ----
    "vp<madcs>wd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemuladd")
     (set_attr "prefix" "vex")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; XOP parallel XMM conditional moves
  (define_insn "xop_pcmov_<mode><avxsizesuffix>"
    [(set (match_operand:V_128_256 0 "register_operand" "=x,x")
  	(if_then_else:V_128_256
! 	  (match_operand:V_128_256 3 "nonimmediate_operand" "x,jm")
  	  (match_operand:V_128_256 1 "register_operand" "x,x")
! 	  (match_operand:V_128_256 2 "nonimmediate_operand" "xjm,x")))]
    "TARGET_XOP"
    "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "<sseinsnmode>")])
  
  ;; Recognize XOP's vpcmov from canonical (xor (and (xor t f) c) f)
***************
*** 26654,26660 ****
  	(plus:V8HI
  	 (any_extend:V8HI
  	  (vec_select:V8QI
! 	   (match_operand:V16QI 1 "nonimmediate_operand" "xm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)
  		      (const_int 8) (const_int 10)
--- 26666,26672 ----
  	(plus:V8HI
  	 (any_extend:V8HI
  	  (vec_select:V8QI
! 	   (match_operand:V16QI 1 "nonimmediate_operand" "xjm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)
  		      (const_int 8) (const_int 10)
***************
*** 26672,26677 ****
--- 26684,26690 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phadd<u>bd"
***************
*** 26680,26686 ****
  	 (plus:V4SI
  	  (any_extend:V4SI
  	   (vec_select:V4QI
! 	    (match_operand:V16QI 1 "nonimmediate_operand" "xm")
  	    (parallel [(const_int 0) (const_int 4)
  		       (const_int 8) (const_int 12)])))
  	  (any_extend:V4SI
--- 26693,26699 ----
  	 (plus:V4SI
  	  (any_extend:V4SI
  	   (vec_select:V4QI
! 	    (match_operand:V16QI 1 "nonimmediate_operand" "xjm")
  	    (parallel [(const_int 0) (const_int 4)
  		       (const_int 8) (const_int 12)])))
  	  (any_extend:V4SI
***************
*** 26705,26710 ****
--- 26718,26724 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phadd<u>bq"
***************
*** 26714,26720 ****
  	  (plus:V2DI
  	   (any_extend:V2DI
  	    (vec_select:V2QI
! 	     (match_operand:V16QI 1 "nonimmediate_operand" "xm")
  	     (parallel [(const_int 0) (const_int 8)])))
  	   (any_extend:V2DI
  	    (vec_select:V2QI
--- 26728,26734 ----
  	  (plus:V2DI
  	   (any_extend:V2DI
  	    (vec_select:V2QI
! 	     (match_operand:V16QI 1 "nonimmediate_operand" "xjm")
  	     (parallel [(const_int 0) (const_int 8)])))
  	   (any_extend:V2DI
  	    (vec_select:V2QI
***************
*** 26754,26759 ****
--- 26768,26774 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phadd<u>wd"
***************
*** 26761,26767 ****
  	(plus:V4SI
  	 (any_extend:V4SI
  	  (vec_select:V4HI
! 	   (match_operand:V8HI 1 "nonimmediate_operand" "xm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)])))
  	 (any_extend:V4SI
--- 26776,26782 ----
  	(plus:V4SI
  	 (any_extend:V4SI
  	  (vec_select:V4HI
! 	   (match_operand:V8HI 1 "nonimmediate_operand" "xjm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)])))
  	 (any_extend:V4SI
***************
*** 26775,26780 ****
--- 26790,26796 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phadd<u>wq"
***************
*** 26783,26789 ****
  	 (plus:V2DI
  	  (any_extend:V2DI
  	   (vec_select:V2HI
! 	    (match_operand:V8HI 1 "nonimmediate_operand" "xm")
  	    (parallel [(const_int 0) (const_int 4)])))
  	  (any_extend:V2DI
  	   (vec_select:V2HI
--- 26799,26805 ----
  	 (plus:V2DI
  	  (any_extend:V2DI
  	   (vec_select:V2HI
! 	    (match_operand:V8HI 1 "nonimmediate_operand" "xjm")
  	    (parallel [(const_int 0) (const_int 4)])))
  	  (any_extend:V2DI
  	   (vec_select:V2HI
***************
*** 26804,26809 ****
--- 26820,26826 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phadd<u>dq"
***************
*** 26811,26817 ****
  	(plus:V2DI
  	 (any_extend:V2DI
  	  (vec_select:V2SI
! 	   (match_operand:V4SI 1 "nonimmediate_operand" "xm")
  	   (parallel [(const_int 0) (const_int 2)])))
  	 (any_extend:V2DI
  	  (vec_select:V2SI
--- 26828,26834 ----
  	(plus:V2DI
  	 (any_extend:V2DI
  	  (vec_select:V2SI
! 	   (match_operand:V4SI 1 "nonimmediate_operand" "xjm")
  	   (parallel [(const_int 0) (const_int 2)])))
  	 (any_extend:V2DI
  	  (vec_select:V2SI
***************
*** 26823,26828 ****
--- 26840,26846 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phsubbw"
***************
*** 26830,26836 ****
  	(minus:V8HI
  	 (sign_extend:V8HI
  	  (vec_select:V8QI
! 	   (match_operand:V16QI 1 "nonimmediate_operand" "xm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)
  		      (const_int 8) (const_int 10)
--- 26848,26854 ----
  	(minus:V8HI
  	 (sign_extend:V8HI
  	  (vec_select:V8QI
! 	   (match_operand:V16QI 1 "nonimmediate_operand" "xjm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)
  		      (const_int 8) (const_int 10)
***************
*** 26848,26853 ****
--- 26866,26872 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phsubwd"
***************
*** 26855,26861 ****
  	(minus:V4SI
  	 (sign_extend:V4SI
  	  (vec_select:V4HI
! 	   (match_operand:V8HI 1 "nonimmediate_operand" "xm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)])))
  	 (sign_extend:V4SI
--- 26874,26880 ----
  	(minus:V4SI
  	 (sign_extend:V4SI
  	  (vec_select:V4HI
! 	   (match_operand:V8HI 1 "nonimmediate_operand" "xjm")
  	   (parallel [(const_int 0) (const_int 2)
  		      (const_int 4) (const_int 6)])))
  	 (sign_extend:V4SI
***************
*** 26869,26874 ****
--- 26888,26894 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_phsubdq"
***************
*** 26876,26882 ****
  	(minus:V2DI
  	 (sign_extend:V2DI
  	  (vec_select:V2SI
! 	   (match_operand:V4SI 1 "nonimmediate_operand" "xm")
  	   (parallel [(const_int 0) (const_int 2)])))
  	 (sign_extend:V2DI
  	  (vec_select:V2SI
--- 26896,26902 ----
  	(minus:V2DI
  	 (sign_extend:V2DI
  	  (vec_select:V2SI
! 	   (match_operand:V4SI 1 "nonimmediate_operand" "xjm")
  	   (parallel [(const_int 0) (const_int 2)])))
  	 (sign_extend:V2DI
  	  (vec_select:V2SI
***************
*** 26888,26893 ****
--- 26908,26914 ----
     (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; XOP permute instructions
***************
*** 26895,26906 ****
    [(set (match_operand:V16QI 0 "register_operand" "=x,x")
  	(unspec:V16QI
  	  [(match_operand:V16QI 1 "register_operand" "x,x")
! 	   (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
! 	   (match_operand:V16QI 3 "nonimmediate_operand" "xm,x")]
  	  UNSPEC_XOP_PERMUTE))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  ;; XOP pack instructions that combine two vectors into a smaller vector
--- 26916,26928 ----
    [(set (match_operand:V16QI 0 "register_operand" "=x,x")
  	(unspec:V16QI
  	  [(match_operand:V16QI 1 "register_operand" "x,x")
! 	   (match_operand:V16QI 2 "nonimmediate_operand" "x,jm")
! 	   (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x")]
  	  UNSPEC_XOP_PERMUTE))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; XOP pack instructions that combine two vectors into a smaller vector
***************
*** 26910,26920 ****
  	 (truncate:V2SI
  	  (match_operand:V2DI 1 "register_operand" "x,x"))
  	 (truncate:V2SI
! 	  (match_operand:V2DI 2 "nonimmediate_operand" "x,m"))))
!    (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_pperm_pack_v4si_v8hi"
--- 26932,26943 ----
  	 (truncate:V2SI
  	  (match_operand:V2DI 1 "register_operand" "x,x"))
  	 (truncate:V2SI
! 	  (match_operand:V2DI 2 "nonimmediate_operand" "x,jm"))))
!    (use (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x"))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_pperm_pack_v4si_v8hi"
***************
*** 26923,26933 ****
  	 (truncate:V4HI
  	  (match_operand:V4SI 1 "register_operand" "x,x"))
  	 (truncate:V4HI
! 	  (match_operand:V4SI 2 "nonimmediate_operand" "x,m"))))
!    (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_pperm_pack_v8hi_v16qi"
--- 26946,26957 ----
  	 (truncate:V4HI
  	  (match_operand:V4SI 1 "register_operand" "x,x"))
  	 (truncate:V4HI
! 	  (match_operand:V4SI 2 "nonimmediate_operand" "x,jm"))))
!    (use (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x"))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_pperm_pack_v8hi_v16qi"
***************
*** 26936,26946 ****
  	 (truncate:V8QI
  	  (match_operand:V8HI 1 "register_operand" "x,x"))
  	 (truncate:V8QI
! 	  (match_operand:V8HI 2 "nonimmediate_operand" "x,m"))))
!    (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x"))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  ;; XOP packed rotate instructions
--- 26960,26971 ----
  	 (truncate:V8QI
  	  (match_operand:V8HI 1 "register_operand" "x,x"))
  	 (truncate:V8QI
! 	  (match_operand:V8HI 2 "nonimmediate_operand" "x,jm"))))
!    (use (match_operand:V16QI 3 "nonimmediate_operand" "xjm,x"))]
    "TARGET_XOP && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
    "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; XOP packed rotate instructions
***************
*** 27011,27017 ****
  (define_insn "xop_rotl<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(rotate:VI_128
! 	 (match_operand:VI_128 1 "nonimmediate_operand" "xm")
  	 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))]
    "TARGET_XOP"
    "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
--- 27036,27042 ----
  (define_insn "xop_rotl<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(rotate:VI_128
! 	 (match_operand:VI_128 1 "nonimmediate_operand" "xjm")
  	 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))]
    "TARGET_XOP"
    "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
***************
*** 27019,27030 ****
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_rotr<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(rotatert:VI_128
! 	 (match_operand:VI_128 1 "nonimmediate_operand" "xm")
  	 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))]
    "TARGET_XOP"
  {
--- 27044,27056 ----
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_rotr<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(rotatert:VI_128
! 	 (match_operand:VI_128 1 "nonimmediate_operand" "xjm")
  	 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))]
    "TARGET_XOP"
  {
***************
*** 27036,27041 ****
--- 27062,27068 ----
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_expand "vrotr<mode>3"
***************
*** 27064,27073 ****
    [(set (match_operand:VI_128 0 "register_operand" "=x,x")
  	(if_then_else:VI_128
  	 (ge:VI_128
! 	  (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
  	  (const_int 0))
  	 (rotate:VI_128
! 	  (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
  	  (match_dup 2))
  	 (rotatert:VI_128
  	  (match_dup 1)
--- 27091,27100 ----
    [(set (match_operand:VI_128 0 "register_operand" "=x,x")
  	(if_then_else:VI_128
  	 (ge:VI_128
! 	  (match_operand:VI_128 2 "nonimmediate_operand" "x,jm")
  	  (const_int 0))
  	 (rotate:VI_128
! 	  (match_operand:VI_128 1 "nonimmediate_operand" "xjm,x")
  	  (match_dup 2))
  	 (rotatert:VI_128
  	  (match_dup 1)
***************
*** 27077,27082 ****
--- 27104,27110 ----
    [(set_attr "type" "sseishft")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; XOP packed shift instructions.
***************
*** 27301,27310 ****
    [(set (match_operand:VI_128 0 "register_operand" "=x,x")
  	(if_then_else:VI_128
  	 (ge:VI_128
! 	  (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
  	  (const_int 0))
  	 (ashift:VI_128
! 	  (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
  	  (match_dup 2))
  	 (ashiftrt:VI_128
  	  (match_dup 1)
--- 27329,27338 ----
    [(set (match_operand:VI_128 0 "register_operand" "=x,x")
  	(if_then_else:VI_128
  	 (ge:VI_128
! 	  (match_operand:VI_128 2 "nonimmediate_operand" "x,jm")
  	  (const_int 0))
  	 (ashift:VI_128
! 	  (match_operand:VI_128 1 "nonimmediate_operand" "xjm,x")
  	  (match_dup 2))
  	 (ashiftrt:VI_128
  	  (match_dup 1)
***************
*** 27314,27329 ****
    [(set_attr "type" "sseishft")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_shl<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x,x")
  	(if_then_else:VI_128
  	 (ge:VI_128
! 	  (match_operand:VI_128 2 "nonimmediate_operand" "x,m")
  	  (const_int 0))
  	 (ashift:VI_128
! 	  (match_operand:VI_128 1 "nonimmediate_operand" "xm,x")
  	  (match_dup 2))
  	 (lshiftrt:VI_128
  	  (match_dup 1)
--- 27342,27358 ----
    [(set_attr "type" "sseishft")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_shl<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x,x")
  	(if_then_else:VI_128
  	 (ge:VI_128
! 	  (match_operand:VI_128 2 "nonimmediate_operand" "x,jm")
  	  (const_int 0))
  	 (ashift:VI_128
! 	  (match_operand:VI_128 1 "nonimmediate_operand" "xjm,x")
  	  (match_dup 2))
  	 (lshiftrt:VI_128
  	  (match_dup 1)
***************
*** 27333,27338 ****
--- 27362,27368 ----
    [(set_attr "type" "sseishft")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_expand "<insn><mode>3"
***************
*** 27404,27416 ****
  (define_insn "xop_frcz<mode>2"
    [(set (match_operand:FMAMODE 0 "register_operand" "=x")
  	(unspec:FMAMODE
! 	 [(match_operand:FMAMODE 1 "nonimmediate_operand" "xm")]
  	 UNSPEC_FRCZ))]
    "TARGET_XOP"
    "vfrcz<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssecvt1")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "<MODE>")])
  
  (define_expand "xop_vmfrcz<mode>2"
--- 27434,27447 ----
  (define_insn "xop_frcz<mode>2"
    [(set (match_operand:FMAMODE 0 "register_operand" "=x")
  	(unspec:FMAMODE
! 	 [(match_operand:FMAMODE 1 "nonimmediate_operand" "xjm")]
  	 UNSPEC_FRCZ))]
    "TARGET_XOP"
    "vfrcz<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssecvt1")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "<MODE>")])
  
  (define_expand "xop_vmfrcz<mode>2"
***************
*** 27428,27434 ****
    [(set (match_operand:VF_128 0 "register_operand" "=x")
  	(vec_merge:VF_128
  	  (unspec:VF_128
! 	   [(match_operand:VF_128 1 "nonimmediate_operand" "xm")]
  	   UNSPEC_FRCZ)
  	  (match_operand:VF_128 2 "const0_operand")
  	  (const_int 1)))]
--- 27459,27465 ----
    [(set (match_operand:VF_128 0 "register_operand" "=x")
  	(vec_merge:VF_128
  	  (unspec:VF_128
! 	   [(match_operand:VF_128 1 "nonimmediate_operand" "xjm")]
  	   UNSPEC_FRCZ)
  	  (match_operand:VF_128 2 "const0_operand")
  	  (const_int 1)))]
***************
*** 27437,27462 ****
    [(set_attr "type" "ssecvt1")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "xop_maskcmp<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(match_operator:VI_128 1 "ix86_comparison_int_operator"
  	 [(match_operand:VI_128 2 "register_operand" "x")
! 	  (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
    "TARGET_XOP"
    "vpcom%Y1<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_maskcmp_uns<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(match_operator:VI_128 1 "ix86_comparison_uns_operator"
  	 [(match_operand:VI_128 2 "register_operand" "x")
! 	  (match_operand:VI_128 3 "nonimmediate_operand" "xm")]))]
    "TARGET_XOP"
    "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
--- 27468,27496 ----
    [(set_attr "type" "ssecvt1")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "xop_maskcmp<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(match_operator:VI_128 1 "ix86_comparison_int_operator"
  	 [(match_operand:VI_128 2 "register_operand" "x")
! 	  (match_operand:VI_128 3 "nonimmediate_operand" "xjm")]))]
    "TARGET_XOP"
    "vpcom%Y1<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_maskcmp_uns<mode>3"
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(match_operator:VI_128 1 "ix86_comparison_uns_operator"
  	 [(match_operand:VI_128 2 "register_operand" "x")
! 	  (match_operand:VI_128 3 "nonimmediate_operand" "xjm")]))]
    "TARGET_XOP"
    "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
***************
*** 27467,27477 ****
  	(unspec:VI_128
  	 [(match_operator:VI_128 1 "ix86_comparison_uns_operator"
  	  [(match_operand:VI_128 2 "register_operand" "x")
! 	   (match_operand:VI_128 3 "nonimmediate_operand" "xm")])]
  	 UNSPEC_XOP_UNSIGNED_CMP))]
    "TARGET_XOP"
    "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  ;; Pcomtrue and pcomfalse support.  These are useless instructions, but are
--- 27501,27512 ----
  	(unspec:VI_128
  	 [(match_operator:VI_128 1 "ix86_comparison_uns_operator"
  	  [(match_operand:VI_128 2 "register_operand" "x")
! 	   (match_operand:VI_128 3 "nonimmediate_operand" "xjm")])]
  	 UNSPEC_XOP_UNSIGNED_CMP))]
    "TARGET_XOP"
    "vpcom%Y1u<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  ;; Pcomtrue and pcomfalse support.  These are useless instructions, but are
***************
*** 27480,27486 ****
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(unspec:VI_128
  	  [(match_operand:VI_128 1 "register_operand" "x")
! 	   (match_operand:VI_128 2 "nonimmediate_operand" "xm")
  	   (match_operand:SI 3 "const_int_operand")]
  	  UNSPEC_XOP_TRUEFALSE))]
    "TARGET_XOP"
--- 27515,27521 ----
    [(set (match_operand:VI_128 0 "register_operand" "=x")
  	(unspec:VI_128
  	  [(match_operand:VI_128 1 "register_operand" "x")
! 	   (match_operand:VI_128 2 "nonimmediate_operand" "xjm")
  	   (match_operand:SI 3 "const_int_operand")]
  	  UNSPEC_XOP_TRUEFALSE))]
    "TARGET_XOP"
***************
*** 27490,27508 ****
  	  : "vpcomfalse<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}");
  }
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_vpermil2<mode>3"
    [(set (match_operand:VF_128_256 0 "register_operand" "=x,x")
  	(unspec:VF_128_256
  	  [(match_operand:VF_128_256 1 "register_operand" "x,x")
! 	   (match_operand:VF_128_256 2 "nonimmediate_operand" "x,m")
! 	   (match_operand:<sseintvecmode> 3 "nonimmediate_operand" "xm,x")
  	   (match_operand:SI 4 "const_0_to_3_operand")]
  	  UNSPEC_VPERMIL2))]
    "TARGET_XOP"
    "vpermil2<ssemodesuffix>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
    [(set_attr "type" "sse4arg")
     (set_attr "mode" "<MODE>")])
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
--- 27525,27545 ----
  	  : "vpcomfalse<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}");
  }
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "TI")])
  
  (define_insn "xop_vpermil2<mode>3"
    [(set (match_operand:VF_128_256 0 "register_operand" "=x,x")
  	(unspec:VF_128_256
  	  [(match_operand:VF_128_256 1 "register_operand" "x,x")
! 	   (match_operand:VF_128_256 2 "nonimmediate_operand" "x,jm")
! 	   (match_operand:<sseintvecmode> 3 "nonimmediate_operand" "xjm,x")
  	   (match_operand:SI 4 "const_0_to_3_operand")]
  	  UNSPEC_VPERMIL2))]
    "TARGET_XOP"
    "vpermil2<ssemodesuffix>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
    [(set_attr "type" "sse4arg")
+    (set_attr "addr" "gpr16")
     (set_attr "mode" "<MODE>")])
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
***************
*** 32039,32053 ****
  })
  
  (define_insn "vpdp<vpdotprodtype>_<mode>"
!   [(set (match_operand:VI4_AVX 0 "register_operand" "=v")
  	(unspec:VI4_AVX
! 	  [(match_operand:VI4_AVX 1 "register_operand" "0")
! 	   (match_operand:VI4_AVX 2 "register_operand" "v")
! 	   (match_operand:VI4_AVX 3 "nonimmediate_operand" "vm")]
  	  VPDOTPROD))]
    "TARGET_AVXVNNIINT8 || TARGET_AVX10_2"
    "vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
!    [(set_attr "prefix" "maybe_evex")])
  
  (define_insn "vpdp<vpdotprodtype>_v16si"
    [(set (match_operand:V16SI 0 "register_operand" "=v")
--- 32076,32092 ----
  })
  
  (define_insn "vpdp<vpdotprodtype>_<mode>"
!   [(set (match_operand:VI4_AVX 0 "register_operand" "=x,v")
  	(unspec:VI4_AVX
! 	  [(match_operand:VI4_AVX 1 "register_operand" "0,0")
! 	   (match_operand:VI4_AVX 2 "register_operand" "x,v")
! 	   (match_operand:VI4_AVX 3 "nonimmediate_operand" "xjm,vm")]
  	  VPDOTPROD))]
    "TARGET_AVXVNNIINT8 || TARGET_AVX10_2"
    "vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
!    [(set_attr "prefix" "maybe_evex")
!     (set_attr "addr" "gpr16,*")
!     (set_attr "isa" "avxvnniint8,avx10_2")])
  
  (define_insn "vpdp<vpdotprodtype>_v16si"
    [(set (match_operand:V16SI 0 "register_operand" "=v")
diff -Nrcpad gcc-15-20260814/gcc/config/rs6000/rs6000-builtin.cc gcc-15-20260821/gcc/config/rs6000/rs6000-builtin.cc
*** gcc-15-20260814/gcc/config/rs6000/rs6000-builtin.cc	Fri Aug 14 22:32:07 2026
--- gcc-15-20260821/gcc/config/rs6000/rs6000-builtin.cc	Fri Aug 21 22:32:07 2026
*************** rs6000_expand_builtin (tree exp, rtx tar
*** 3360,3365 ****
--- 3360,3369 ----
  
        // 0: Boolean return (Output)
        struct expand_operand ops[8];
+       // Make sure we always have a place for bool operand.
+       if (target == const0_rtx || !target)
+ 	target = gen_reg_rtx (SImode);
+ 
        create_output_operand (&ops[0], target, SImode);
  
        // 1: Old value return (Output)
diff -Nrcpad gcc-15-20260814/gcc/config/rs6000/rs6000-c.cc gcc-15-20260821/gcc/config/rs6000/rs6000-c.cc
*** gcc-15-20260814/gcc/config/rs6000/rs6000-c.cc	Fri Aug 14 22:32:07 2026
--- gcc-15-20260821/gcc/config/rs6000/rs6000-c.cc	Fri Aug 21 22:32:07 2026
*************** altivec_resolve_overloaded_builtin (loca
*** 1732,1772 ****
  	    error_at (loc, "%qE requires 6 arguments", fndecl);
  	  return error_mark_node;
  	}
  
!       /* Get the first argument to determine the actual type.  */
!       tree arg0 = (*arglist)[0];
!       tree type0 = TREE_TYPE (arg0);
! 
!       /* Must be a pointer.  */
!       if (!POINTER_TYPE_P (type0))
! 	{
! 	  if (complain)
! 	    error_at (loc, "first argument to %qE must be a pointer", fndecl);
! 	  return error_mark_node;
! 	}
  
!       /* Get the pointee type.  */
!       tree pointee_type = TREE_TYPE (type0);
  
!       /* Must be a complete type.  */
!       if (!COMPLETE_TYPE_P (pointee_type))
! 	{
! 	  if (complain)
! 	    error_at (loc, "first argument to %qE must point to a complete"
! 		      " type", fndecl);
! 	  return error_mark_node;
! 	}
  
!       /* Get size in bytes.  */
!       tree size_tree = TYPE_SIZE_UNIT (pointee_type);
!       if (!tree_fits_uhwi_p (size_tree))
! 	{
  	  if (complain)
! 	    error_at (loc, "type size must be constant");
  	  return error_mark_node;
  	}
! 
!       unsigned HOST_WIDE_INT size = tree_to_uhwi (size_tree);
  
        /* Determine which size-specific builtin to use.  */
        rs6000_gen_builtins target_fcode;
--- 1732,1786 ----
  	    error_at (loc, "%qE requires 6 arguments", fndecl);
  	  return error_mark_node;
  	}
+       unsigned HOST_WIDE_INT size;
+       for (int i=0; i<3; i++) {
+ 	/* Get the first argument to determine the actual type.  */
+ 	tree arg0 = (*arglist)[i];
+ 	tree type0 = TREE_TYPE (arg0);
  
! 	/* Must be a pointer.  */
! 	if (!POINTER_TYPE_P (type0))
! 	  {
! 	    if (complain)
! 	      error_at (loc, "argument %d to %qE must be a pointer",
! 			i + 1, fndecl);
! 	    return error_mark_node;
! 	  }
  
! 	/* Get the pointee type.  */
! 	tree pointee_type = TREE_TYPE (type0);
  
! 	/* Must be a complete type.  */
! 	if (!COMPLETE_TYPE_P (pointee_type))
! 	  {
! 	    if (complain)
! 	      error_at (loc, "argument %d to %qE must point to a complete"
! 			" type", i + 1, fndecl);
! 	    return error_mark_node;
! 	  }
! 	if (FUNCTION_POINTER_TYPE_P (type0))
! 	  {
! 	    if (complain)
! 	      error_at (loc, "argument %d to %qE must not be a pointer to a"
! 			" function", i + 1, fndecl);
! 	    return error_mark_node;
! 	  }
  
! 	/* Get size in bytes.  */
! 	tree size_tree = TYPE_SIZE_UNIT (pointee_type);
! 	if (!tree_fits_uhwi_p (size_tree))
! 	  {
! 		if (complain)
! 		error_at (loc, "type size must be constant");
! 		return error_mark_node;
! 	  }
! 	if (i > 0 && size != tree_to_uhwi (size_tree)) {
  	  if (complain)
! 	    error_at(loc, "size mismatch in argument %d", i + 1);
  	  return error_mark_node;
  	}
! 	size = tree_to_uhwi (size_tree);
!       }
  
        /* Determine which size-specific builtin to use.  */
        rs6000_gen_builtins target_fcode;
*************** altivec_resolve_overloaded_builtin (loca
*** 1791,1796 ****
--- 1805,1817 ----
  	  int_type = long_long_unsigned_type_node;
  	  break;
  	case 16:
+ 	  if (!TARGET_QUAD_MEMORY_ATOMIC)
+ 	    {
+ 	      if (complain)
+ 		error_at (loc, "%qE requires the %qs option for 16-byte operands",
+ 			  fndecl, "-mquad-memory-atomic");
+ 	      return error_mark_node;
+ 	    }
  	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_TI;
  	  int_type = unsigned_intTI_type_node;
  	  break;
diff -Nrcpad gcc-15-20260814/gcc/fortran/ChangeLog gcc-15-20260821/gcc/fortran/ChangeLog
*** gcc-15-20260814/gcc/fortran/ChangeLog	Fri Aug 14 22:32:07 2026
--- gcc-15-20260821/gcc/fortran/ChangeLog	Fri Aug 21 22:32:08 2026
***************
*** 1,3 ****
--- 1,21 ----
+ 2026-08-16  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-03-27  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/114021
+ 	* symbol.cc (gfc_get_unique_symtree): If the namespace argument
+ 	is NULL, allocate a new symtree and provide it with the unique
+ 	name.
+ 	* trans-expr.cc (trans_scalar_assign): In the deep copy of a
+ 	derived type with allocatable components, fix the rhs value if
+ 	it is not a constant or a variable.
+ 	* trans-stmt.cc (gfc_trans_allocate): Do not deallocate
+ 	allocatable components of a source that is not a variable and
+ 	is a pointer. If the DECL_NAME or its IDENTIFIER_POINTER are
+ 	null,use gfc_get_unique_symtree with NULL namespace to obtain a
+ 	symtree for the assignment.
+ 
  2026-08-08  Paul Thomas  <pault@gcc.gnu.org>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260814/gcc/fortran/symbol.cc gcc-15-20260821/gcc/fortran/symbol.cc
*** gcc-15-20260814/gcc/fortran/symbol.cc	Fri Aug 14 22:32:08 2026
--- gcc-15-20260821/gcc/fortran/symbol.cc	Fri Aug 21 22:32:08 2026
*************** gfc_get_unique_symtree (gfc_namespace *n
*** 3090,3096 ****
    static int serial = 0;
  
    sprintf (name, "@%d", serial++);
!   return gfc_new_symtree (&ns->sym_root, name);
  }
  
  
--- 3090,3104 ----
    static int serial = 0;
  
    sprintf (name, "@%d", serial++);
!   if (ns)
!     return gfc_new_symtree (&ns->sym_root, name);
!   else
!     {
!       /* Some uses need a symtree that is cleaned up locally.  */
!       gfc_symtree *st = XCNEW (gfc_symtree);
!       st->name = gfc_get_string ("%s", name);
!       return st;
!     }
  }
  
  
diff -Nrcpad gcc-15-20260814/gcc/fortran/trans-expr.cc gcc-15-20260821/gcc/fortran/trans-expr.cc
*** gcc-15-20260814/gcc/fortran/trans-expr.cc	Fri Aug 14 22:32:08 2026
--- gcc-15-20260821/gcc/fortran/trans-expr.cc	Fri Aug 21 22:32:08 2026
*************** gfc_trans_scalar_assign (gfc_se *lse, gf
*** 11601,11606 ****
--- 11601,11608 ----
        /* Are the rhs and the lhs the same?  */
        if (deep_copy)
  	{
+ 	  if (!TREE_CONSTANT (rse->expr) && !VAR_P (rse->expr))
+ 	    rse->expr = gfc_evaluate_now (rse->expr, &rse->pre);
  	  cond = fold_build2_loc (input_location, EQ_EXPR, logical_type_node,
  				  gfc_build_addr_expr (NULL_TREE, lse->expr),
  				  gfc_build_addr_expr (NULL_TREE, rse->expr));
diff -Nrcpad gcc-15-20260814/gcc/fortran/trans-stmt.cc gcc-15-20260821/gcc/fortran/trans-stmt.cc
*** gcc-15-20260814/gcc/fortran/trans-stmt.cc	Fri Aug 14 22:32:08 2026
--- gcc-15-20260821/gcc/fortran/trans-stmt.cc	Fri Aug 21 22:32:08 2026
*************** gfc_trans_allocate (gfc_code * code, gfc
*** 6777,6782 ****
--- 6777,6783 ----
  	  && (code->expr3->expr_type != EXPR_VARIABLE || temp_obj_created)
  	  && code->expr3->ts.u.derived->attr.alloc_comp
  	  && !code->expr3->must_finalize
+ 	  && !gfc_expr_attr (code->expr3).pointer
  	  && !code->ext.alloc.expr3_not_explicit)
  	{
  	  tmp = gfc_deallocate_alloc_comp (code->expr3->ts.u.derived,
*************** gfc_trans_allocate (gfc_code * code, gfc
*** 6940,6950 ****
  	  /* Build a temporary symtree and symbol.  Do not add it to the current
  	     namespace to prevent accidentaly modifying a colliding
  	     symbol's as.  */
- 	  newsym = XCNEW (gfc_symtree);
  	  /* The name of the symtree should be unique, because gfc_create_var ()
  	     took care about generating the identifier.  */
! 	  newsym->name
! 	    = gfc_get_string ("%s", IDENTIFIER_POINTER (DECL_NAME (expr3)));
  	  newsym->n.sym = gfc_new_symbol (newsym->name, NULL);
  	  /* The backend_decl is known.  It is expr3, which is inserted
  	     here.  */
--- 6941,6956 ----
  	  /* Build a temporary symtree and symbol.  Do not add it to the current
  	     namespace to prevent accidentaly modifying a colliding
  	     symbol's as.  */
  	  /* The name of the symtree should be unique, because gfc_create_var ()
  	     took care about generating the identifier.  */
! 	  if (DECL_NAME (expr3) && IDENTIFIER_POINTER (DECL_NAME (expr3)))
! 	    {
! 	      const char *name = IDENTIFIER_POINTER (DECL_NAME (expr3));
! 	      newsym = XCNEW (gfc_symtree);
! 	      newsym->name = gfc_get_string ("%s", name);
! 	    }
! 	  else
! 	    newsym = gfc_get_unique_symtree (NULL);
  	  newsym->n.sym = gfc_new_symbol (newsym->name, NULL);
  	  /* The backend_decl is known.  It is expr3, which is inserted
  	     here.  */
diff -Nrcpad gcc-15-20260814/gcc/testsuite/ChangeLog gcc-15-20260821/gcc/testsuite/ChangeLog
*** gcc-15-20260814/gcc/testsuite/ChangeLog	Fri Aug 14 22:32:10 2026
--- gcc-15-20260821/gcc/testsuite/ChangeLog	Fri Aug 21 22:32:10 2026
***************
*** 1,3 ****
--- 1,97 ----
+ 2026-08-20  Hongyu Wang  <hongyu.wang@intel.com>
+ 
+ 	Backported from master:
+ 	2026-08-12  Hongyu Wang  <hongyu.wang@intel.com>
+ 
+ 	PR target/126787
+ 	* gcc.target/i386/pr126787.c: New test.
+ 
+ 2026-08-20  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-08-10  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	PR target/126513
+ 	* gcc.target/powerpc/pr126513-acmp-tst-1.c: New test.
+ 	* gcc.target/powerpc/pr126513-acmp-tst-2.c: New test.
+ 	* gcc.target/powerpc/pr126513-acmp-tst-3.c: New test.
+ 
+ 2026-08-19  Alice Carlotti  <alice.carlotti@arm.com>
+ 
+ 	PR target/124629
+ 	* gcc.target/aarch64/cpunative/info_36: New test file.
+ 	* gcc.target/aarch64/cpunative/native_cpu_36.c: New test.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-08-05  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/126650
+ 	* gcc.dg/torture/pr126650.c: New testcase.
+ 
+ 2026-08-19  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2026-07-28  H.J. Lu  <hjl.tools@gmail.com>
+ 		    Richard Biener   <rguenther@suse.de>
+ 
+ 	PR middle-end/126410
+ 	* gcc.target/i386/pr126410-1a.c: New test.
+ 	* gcc.target/i386/pr126410-1b.c: Likewise.
+ 	* gcc.target/i386/pr126410-1c.c: Likewise.
+ 	* gcc.target/i386/pr126410-2a.c: Likewise.
+ 	* gcc.target/i386/pr126410-2b.c: Likewise.
+ 	* gcc.target/i386/pr126410-2c.c: Likewise.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-06-15  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/125786
+ 	* gcc.dg/torture/pr125786.c: New testcase.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-06-02  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/125545
+ 	* gcc.dg/torture/pr125545.c: New testcase.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-06-03  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR tree-optimization/125477
+ 	* gcc.dg/torture/pr125477.c: New testcase.
+ 
+ 2026-08-19  Richard Biener  <rguenther@suse.de>
+ 
+ 	Backported from master:
+ 	2026-05-04  Richard Biener  <rguenther@suse.de>
+ 
+ 	PR middle-end/125156
+ 	* gcc.dg/torture/pr125156.c: New testcase.
+ 
+ 2026-08-19  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	Backported from master:
+ 	2026-06-26  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	PR target/125949
+ 	* gcc.target/i386/pr125949.c: New test.
+ 
+ 2026-08-16  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-03-27  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/114021
+ 	* gfortran.dg/pr114021.f90: New test.
+ 
  2026-08-11  Robin Dapp  <robin.dapp@oss.qualcomm.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125156.c gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125156.c
*** gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125156.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125156.c	Fri Aug 21 22:32:13 2026
***************
*** 0 ****
--- 1,26 ----
+ /* { dg-do compile } */
+ 
+ #include <stdint.h>
+ 
+ int64_t g1, g8;
+ 
+ void g14()
+ {
+   int16_t v5;
+   goto lbl_cont30;
+ lbl_bf2:
+   g8 = 0;
+ lbl_b5:
+   g1 = g1 - 8366249724514421075;
+   switch (v5)
+ case 5:
+ case 2:
+     goto lbl_b5;
+     goto lbl_bf2;
+ lbl_cont30:
+     switch (v5)
+       {
+       case 0: goto lbl_bf2;
+       case 5: goto lbl_b5;
+       }
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125477.c gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125477.c
*** gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125477.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125477.c	Fri Aug 21 22:32:13 2026
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ 
+ void f123(void) __attribute__((__returns_twice__));
+ int c;
+ volatile int i;
+ void e(long *a, long *d, int f) {
+ g:
+   if (i)
+     return;
+   f123();
+   for (;;) {
+     __asm__ goto("" : : : : g);
+     c = 0;
+     for (; c < f; c++)
+       a[c] = d[c];
+   }
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125545.c gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125545.c
*** gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125545.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125545.c	Fri Aug 21 22:32:13 2026
***************
*** 0 ****
--- 1,9 ----
+ /* { dg-do compile } */
+ 
+ int b(int c)
+ {
+   int a;
+   __asm__ goto("" : "=r"(a) : : : d);
+ d:
+   return c && a != 42 && a >= 42;
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125786.c gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125786.c
*** gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr125786.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr125786.c	Fri Aug 21 22:32:13 2026
***************
*** 0 ****
--- 1,30 ----
+ /* { dg-do run } */
+ 
+ #define length 16
+ typedef int type;
+ typedef type v8i64 __attribute__((vector_size(sizeof(type)*length)));
+ v8i64 g6, g27;
+ _Bool main_c14;
+ 
+ __attribute__((noipa))
+ static
+ void f(v8i64 *a)
+ {
+   for(int i =0;i<length;i++)
+     if ((*a)[i] != -1)
+       __builtin_abort();
+ }
+ 
+ int main()
+ {
+   if (main_c14) goto lbl_br43;
+ lbl_bf7:
+   g6 = 0 <= g27;
+   g27 = g27 <= g27;
+   g27 = g6 > g27;
+ lbl_br43:
+   g6 = g6 | g27;
+   if (main_c14) goto lbl_bf7;
+   g6 = g6 * g27 == 0;
+   f(&g6);
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr126650.c gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr126650.c
*** gcc-15-20260814/gcc/testsuite/gcc.dg/torture/pr126650.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.dg/torture/pr126650.c	Fri Aug 21 22:32:13 2026
***************
*** 0 ****
--- 1,35 ----
+ /* { dg-do run } */
+ 
+ #include <stdarg.h>
+ #include <stdlib.h>
+ 
+ long a;
+ 
+ void __attribute__((noipa)) foo (int n, ...)
+ {
+   va_list list;
+   va_start (list, n);
+   int val = va_arg (list, int);
+   if (val != -64)
+     abort ();
+   va_end (list);
+ }
+ 
+ int main()
+ {
+   struct b {
+     int : 7;
+     int : 2;
+     int : 6;
+     int : 3;
+     int c : 7;
+   };
+   union {
+     int d;
+     struct b bf;
+     char e[4];
+   } f;
+   f.d = a;
+   f.e[3] = 7;
+   foo (1, f.bf.c);
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/aarch64/cpunative/info_36 gcc-15-20260821/gcc/testsuite/gcc.target/aarch64/cpunative/info_36
*** gcc-15-20260814/gcc/testsuite/gcc.target/aarch64/cpunative/info_36	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/aarch64/cpunative/info_36	Fri Aug 21 22:32:13 2026
***************
*** 0 ****
--- 1,9 ----
+ processor	: 0
+ BogoMIPS	: 100.00
+ Features	: fp asimd evtstrm aes pmull sha1 sha2 crc32 asimddp sve sve2 fphp asimdhp fcma
+ CPU implementer	: 0x41
+ CPU architecture: 8
+ CPU variant	: 0x0
+ CPU part	: 0xd08
+ CPU revision	: 2
+ 
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_36.c gcc-15-20260821/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_36.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_36.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/aarch64/cpunative/native_cpu_36.c	Fri Aug 21 22:32:13 2026
***************
*** 0 ****
--- 1,10 ----
+ /* { dg-do compile { target { { aarch64*-*-linux*} && native } } } */
+ /* { dg-set-compiler-env-var GCC_CPUINFO "$srcdir/gcc.target/aarch64/cpunative/info_36" } */
+ /* { dg-additional-options "-march=native -mtune=cortex-a34" } */
+ 
+ int main()
+ {
+   return 0;
+ }
+ 
+ /* { dg-final { scan-assembler {\.arch armv8-a\+dotprod\+crc\+crypto\+sve2\n} } } */
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr125949.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr125949.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr125949.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr125949.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,38 ----
+ /* PR target/125949 */
+ /* On a target with AVX-VNNI-INT8 the vpdpb{ss,su,uu}d[s] instructions only
+    have a VEX encoding.  Even under register pressure the compiler must stay
+    within xmm/ymm0-15 for these insns and must not allocate xmm/ymm16-31 and
+    emit an EVEX-encoded vpdpb* using a high register.  -mavx512vl exposes the
+    xmm/ymm16-31 register file so the allocator would otherwise be tempted to
+    use it.  */
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -mavxvnniint8 -mavx512vl" } */
+ /* { dg-final { scan-assembler-not "vpdpb\[a-z\]+\[ \\t\]+\[^\n\]*%\[xy\]mm(1\[6-9\]|2\[0-9\]|3\[01\])" } } */
+ 
+ #include <immintrin.h>
+ 
+ #define NACC 32
+ 
+ void
+ foo (unsigned int *restrict out, const unsigned char *restrict a,
+      const unsigned char *restrict b, int n)
+ {
+   __m256i acc[NACC];
+ 
+   for (int k = 0; k < NACC; k++)
+     acc[k] = _mm256_setzero_si256 ();
+ 
+   for (int i = 0; i < n; i++)
+     {
+       __m256i vb = _mm256_loadu_si256 ((const __m256i *) (b + 32 * (i & 7)));
+       for (int k = 0; k < NACC; k++)
+ 	{
+ 	  __m256i va
+ 	    = _mm256_loadu_si256 ((const __m256i *) (a + 32 * ((i + k) & 15)));
+ 	  acc[k] = _mm256_dpbuud_epi32 (acc[k], va, vb);
+ 	}
+     }
+ 
+   for (int k = 0; k < NACC; k++)
+     _mm256_storeu_si256 ((__m256i *) (out + 8 * k), acc[k]);
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-1a.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-1a.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-1a.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-1a.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,22 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -march=x86-64-v4 -fomit-frame-pointer" } */
+ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+ 
+ #ifndef N
+ #define N 4
+ #endif
+ 
+ typedef float vector[N];
+ 
+ extern vector v;
+ 
+ extern void foo (vector *);
+ 
+ void
+ func (vector a, vector b)
+ {
+   vector r;
+   for (int i = 0; i < N; i++)
+     r[i] = a[i] * b[i];
+   foo (&r);
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-1b.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-1b.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-1b.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-1b.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,8 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -march=x86-64-v4 -fomit-frame-pointer" } */
+ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-32,\[\\t \]*%\[re\]?sp" } } */
+ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+ 
+ #define N 8
+ 
+ #include "pr126410-1a.c"
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-1c.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-1c.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-1c.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-1c.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,7 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -march=x86-64-v4 -fomit-frame-pointer" } */
+ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+ 
+ #define N 16
+ 
+ #include "pr126410-1a.c"
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-2a.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-2a.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-2a.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-2a.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,22 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -march=x86-64-v4 -fomit-frame-pointer" } */
+ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+ 
+ #ifndef N
+ #define N 4
+ #endif
+ 
+ typedef struct { float values[N]; } vector;
+ 
+ extern vector v;
+ 
+ extern void foo (vector *);
+ 
+ void
+ func (vector a, vector b)
+ {
+   vector r;
+   for (int i = 0; i < N; i++)
+     r.values[i] = a.values[i] * b.values[i];
+   foo (&r);
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-2b.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-2b.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-2b.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-2b.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,8 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -march=x86-64-v4 -fomit-frame-pointer" } */
+ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-32,\[\\t \]*%\[re\]?sp" } } */
+ /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+ 
+ #define N 8
+ 
+ #include "pr126410-2a.c"
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-2c.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-2c.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126410-2c.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126410-2c.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,7 ----
+ /* { dg-do compile { target *-*-linux* } } */
+ /* { dg-options "-O2 -march=x86-64-v4 -fomit-frame-pointer" } */
+ /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
+ 
+ #define N 16
+ 
+ #include "pr126410-2a.c"
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126787.c gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126787.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/i386/pr126787.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/i386/pr126787.c	Fri Aug 21 22:32:14 2026
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do assemble { target { apxf && { ! ia32 } } } } */
+ /* { dg-options "-O2 -mapxf -mprefer-avx128 -funroll-loops --param max-unroll-times=4 -ffast-math -ftree-vectorize" } */
+ 
+ typedef float f4;
+ __attribute__((__target__("avx,fma4")))
+ void smm_avx128_fma4(f4 * restrict c, const f4 * restrict a,
+                      const f4 * restrict b, int m, int n, int k)
+ {
+     for (int j = 0; j < n; j++)
+         for (int l = 0; l < k; l++) {
+             f4 bl = b[l + j*k];
+             for (int i = 0; i < m; i++)
+                 c[i + j*m] += a[i + l*m] * bl;
+         }
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-1.c gcc-15-20260821/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-1.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-1.c	Fri Aug 21 22:32:15 2026
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+ 
+ // Need power8 for l<b,h,q>arx
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ __int128 word_exchange_uti_ptr;
+ int word_exchange_uti_expected;
+ unsigned word_exchange_uti_desired() {
+   __builtin_ppc_atomic_cas_local( /* { dg-error "argument 2 to '__builtin_ppc_atomic_cas_local' must be a pointer" } */
+       &word_exchange_uti_ptr, word_exchange_uti_expected,
+       word_exchange_uti_desired, 0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ unsigned word_exchange_uti_desired_fptr() {
+   __builtin_ppc_atomic_cas_local( /* { dg-error "argument 1 to '__builtin_ppc_atomic_cas_local' must not be a pointer to a function" } */
+       &word_exchange_uti_desired_fptr, &word_exchange_uti_desired,
+       &word_exchange_uti_desired_fptr, 0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ unsigned word_exchange_uti_desired_mismatch() {
+   __builtin_ppc_atomic_cas_local( /* { dg-error "size mismatch in argument 2" } */
+       &word_exchange_uti_ptr, &word_exchange_uti_expected,
+       &word_exchange_uti_ptr, 0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-2.c gcc-15-20260821/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-2.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-2.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-2.c	Fri Aug 21 22:32:15 2026
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+ 
+ // Need power8 for l<b,h,q>arx
+ /* { dg-options "-O2 -mdejagnu-cpu=power8 -mno-quad-memory-atomic" } */
+ 
+ __int128 word_exchange_uti_ptr;
+ __int128 word_exchange_uti_ptr_expected;
+ __int128 word_exchange_uti_ptr_desired;
+ 
+ unsigned word_exchange_uti_desired() {
+   __builtin_ppc_atomic_cas_local( /* { dg-error "'__builtin_ppc_atomic_cas_local' requires the '-mquad-memory-atomic' option for 16-byte operands" } */
+       &word_exchange_uti_ptr, &word_exchange_uti_ptr_expected,
+       &word_exchange_uti_ptr_desired, 0, __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-3.c gcc-15-20260821/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-3.c
*** gcc-15-20260814/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-3.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gcc.target/powerpc/pr126513-acmp-tst-3.c	Fri Aug 21 22:32:15 2026
***************
*** 0 ****
--- 1,176 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+ 
+ // Need power8 for l<b,h,q>arx
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ typedef struct udt_1
+ {
+   char *a;
+ } udt_1t;
+ typedef struct udt_2
+ {
+   char a;
+   char b;
+ } udt_2t;
+ typedef struct udt_4
+ {
+   short a;
+   short b;
+ } udt_4t;
+ typedef struct udt_8
+ {
+   int a;
+   int b;
+ } udt_8t;
+ typedef struct udt_16
+ {
+   long long a;
+   long long b;
+ } udt_16t;
+ void
+ word_exchange_nqi (char *ptr, char *expected, char *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_qi (signed char *ptr, signed char *expected, signed char *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_uqi (unsigned char *ptr, unsigned char *expected,
+                    unsigned char *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_hi (short *ptr, short *expected, short *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_shi (signed short *ptr, signed short *expected,
+                    signed short *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_uhi (unsigned short *ptr, unsigned short *expected,
+                    unsigned short *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_si (int *ptr, int *expected, int *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_ssi (signed int *ptr, signed int *expected, signed int *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_usi (unsigned int *ptr, unsigned int *expected,
+                    unsigned int *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_di (long long *ptr, long long *expected, long long *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_sdi (signed long long *ptr, signed long long *expected,
+                    signed long long *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_udi (unsigned long long *ptr, unsigned long long *expected,
+                    unsigned long long *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_sti (signed __int128 *ptr, signed __int128 *expected,
+                    signed __int128 *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_uti (unsigned __int128 *ptr, unsigned __int128 *expected,
+                    unsigned __int128 *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_f32 (float *ptr, float *expected, float *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_f64 (double *ptr, double *expected, double *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_f128 (__ieee128 *ptr, __ieee128 *expected, __ieee128 *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_udt_1 (udt_1t *ptr, udt_1t *expected, udt_1t *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_udt_2 (udt_2t *ptr, udt_2t *expected, udt_2t *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_udt_4 (udt_4t *ptr, udt_4t *expected, udt_4t *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_udt_8 (udt_8t *ptr, udt_8t *expected, udt_8t *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ void
+ word_exchange_udt_16 (udt_16t *ptr, udt_16t *expected, udt_16t *desired)
+ {
+   __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */
+ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 4 } } */
+ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 5 } } */
+ /* { dg-final { scan-assembler-times {\mldarx +[0-9]+,[0-9]+,[0-9]+,1} 6 } } */
+ /* { dg-final { scan-assembler-times {\mlqarx +[0-9]+,[0-9]+,[0-9]+,1} 4 } } */
diff -Nrcpad gcc-15-20260814/gcc/testsuite/gfortran.dg/pr114021.f90 gcc-15-20260821/gcc/testsuite/gfortran.dg/pr114021.f90
*** gcc-15-20260814/gcc/testsuite/gfortran.dg/pr114021.f90	Thu Jan  1 00:00:00 1970
--- gcc-15-20260821/gcc/testsuite/gfortran.dg/pr114021.f90	Fri Aug 21 22:32:16 2026
***************
*** 0 ****
--- 1,64 ----
+ ! { dg-do run }
+ !
+ ! Test the fix for PR114021 in which the ALLOCATE statement caused an ICE.
+ ! The test checks that f() is called once per allocation, that the result
+ ! of the allocation is correct and that a deep copy of w%x1 has been effected
+ ! in 's2' without freeing it. 's3' is a variant, which produced no fewer than
+ ! three calls to f() in the course of the assignment and the deep copy of
+ ! the allocatable component.
+ !
+ ! Contributed by Steve Kargl  <kargl@gcc.gnu.org>
+ !
+ module m1
+    type y
+       integer, allocatable:: x1(:)
+    end type
+    type(y), target :: w
+    integer :: c = 0
+ contains
+    function f()
+       type(y), pointer :: f
+       f => w
+       c = c + 1
+    end function
+ end
+ 
+ subroutine s1
+    use m1
+    type(y), allocatable :: x
+    allocate(x, source = f())
+    if ((c /= 1) .or. (allocated (x%x1))) stop 1
+ end
+ 
+ subroutine s2
+    use m1
+    type(y), pointer :: x
+    allocate(x, source = f())
+    if ((c /= 2) .or. (.not.allocated (x%x1))) stop 2
+    if (any (abs (x%x1 - [3.0,4.0]) > 1e-6)) stop 3
+    x%x1 = [5.0,6.0]
+    if (allocated (x%x1)) deallocate (x%x1)
+    if (associated (x)) deallocate (x)
+ end
+ 
+ subroutine s3
+   use m1
+   implicit none
+   type(y), allocatable :: x
+   allocate (x)
+   x = f()
+   if (any (abs (x%x1 - [3.0,4.0]) > 1e-6)) stop 4
+ end
+ 
+    use m1
+    call s1
+    w%x1 = [1.0,2.0]
+    if (c /= 1) stop 5
+    w%x1 = [3.0,4.0]
+    call s2
+    if (c /= 2) stop 6
+    call s3
+    if (c /= 3) stop 7
+    if (.not.allocated (w%x1) .or. any (abs (w%x1 - [3.0,4.0]) > 1e-6)) stop 8
+    if (allocated (w%x1)) deallocate (w%x1)
+ end
diff -Nrcpad gcc-15-20260814/gcc/tree-affine.cc gcc-15-20260821/gcc/tree-affine.cc
*** gcc-15-20260814/gcc/tree-affine.cc	Fri Aug 14 22:32:16 2026
--- gcc-15-20260821/gcc/tree-affine.cc	Fri Aug 21 22:32:17 2026
*************** get_inner_reference_aff (tree ref, aff_t
*** 1030,1039 ****
        aff_combination_add (addr, &tmp);
      }
  
!   aff_combination_const (&tmp, sizetype, bits_to_bytes_round_down (bitpos));
    aff_combination_add (addr, &tmp);
  
!   *size = bits_to_bytes_round_up (bitsize);
  
    return base;
  }
--- 1030,1040 ----
        aff_combination_add (addr, &tmp);
      }
  
!   poly_int64 bytepos = bits_to_bytes_round_down (bitpos);
!   aff_combination_const (&tmp, sizetype, bytepos);
    aff_combination_add (addr, &tmp);
  
!   *size = bits_to_bytes_round_up (bitpos + bitsize) - bytepos;
  
    return base;
  }
diff -Nrcpad gcc-15-20260814/gcc/tree-cfgcleanup.cc gcc-15-20260821/gcc/tree-cfgcleanup.cc
*** gcc-15-20260814/gcc/tree-cfgcleanup.cc	Fri Aug 14 22:32:16 2026
--- gcc-15-20260821/gcc/tree-cfgcleanup.cc	Fri Aug 21 22:32:17 2026
*************** cleanup_control_expr_graph (basic_block
*** 200,206 ****
  
    bitmap_set_bit (cfgcleanup_altered_bbs, bb->index);
    gsi_remove (&gsi, true);
!   taken_edge->flags = EDGE_FALLTHRU;
  
    return retval;
  }
--- 200,207 ----
  
    bitmap_set_bit (cfgcleanup_altered_bbs, bb->index);
    gsi_remove (&gsi, true);
!   taken_edge->flags &= ~(EDGE_TRUE_VALUE|EDGE_FALSE_VALUE);
!   taken_edge->flags |= EDGE_FALLTHRU;
  
    return retval;
  }
diff -Nrcpad gcc-15-20260814/gcc/tree-ssa-reassoc.cc gcc-15-20260821/gcc/tree-ssa-reassoc.cc
*** gcc-15-20260814/gcc/tree-ssa-reassoc.cc	Fri Aug 14 22:32:16 2026
--- gcc-15-20260821/gcc/tree-ssa-reassoc.cc	Fri Aug 21 22:32:17 2026
*************** insert_stmt_after (gimple *stmt, gimple
*** 1521,1527 ****
        return;
      }
    else if (gimple_code (insert_point) == GIMPLE_ASM
! 	   && gimple_asm_nlabels (as_a <gasm *> (insert_point)) != 0)
      /* We have no idea where to insert - it depends on where the
         uses will be placed.  */
      gcc_unreachable ();
--- 1521,1528 ----
        return;
      }
    else if (gimple_code (insert_point) == GIMPLE_ASM
! 	   && gimple_asm_nlabels (as_a <gasm *> (insert_point)) != 0
! 	   && !single_succ_p (gimple_bb (insert_point)))
      /* We have no idea where to insert - it depends on where the
         uses will be placed.  */
      gcc_unreachable ();
*************** optimize_vec_cond_expr (tree_code opcode
*** 4271,4277 ****
  
    for (i = 0; i < length; ++i)
      {
!       tree elt0 = (*ops)[i]->op;
  
        gassign *stmt0, *vcond0;
        bool invert;
--- 4272,4278 ----
  
    for (i = 0; i < length; ++i)
      {
!       tree &elt0 = (*ops)[i]->op;
  
        gassign *stmt0, *vcond0;
        bool invert;
*************** optimize_vec_cond_expr (tree_code opcode
*** 4319,4329 ****
  	  gimple_stmt_iterator gsi = gsi_for_stmt (vcond0);
  	  tree exp = force_gimple_operand_gsi (&gsi, comb, true, NULL_TREE,
  					       true, GSI_SAME_STMT);
! 	  if (invert)
! 	    swap_ssa_operands (vcond0, gimple_assign_rhs2_ptr (vcond0),
! 			       gimple_assign_rhs3_ptr (vcond0));
! 	  gimple_assign_set_rhs1 (vcond0, exp);
! 	  update_stmt (vcond0);
  
  	  elt1 = error_mark_node;
  	  any_changes = true;
--- 4320,4332 ----
  	  gimple_stmt_iterator gsi = gsi_for_stmt (vcond0);
  	  tree exp = force_gimple_operand_gsi (&gsi, comb, true, NULL_TREE,
  					       true, GSI_SAME_STMT);
! 	  tree res = gimple_build (&gsi, true, GSI_SAME_STMT, UNKNOWN_LOCATION,
! 				   VEC_COND_EXPR, TREE_TYPE (elt0), exp,
! 				   constant_boolean_node (true,
! 							  TREE_TYPE (elt0)),
! 				   constant_boolean_node (false,
! 							  TREE_TYPE (elt0)));
! 	  elt0 = res;
  
  	  elt1 = error_mark_node;
  	  any_changes = true;
diff -Nrcpad gcc-15-20260814/gcc/tree-vect-loop-manip.cc gcc-15-20260821/gcc/tree-vect-loop-manip.cc
*** gcc-15-20260814/gcc/tree-vect-loop-manip.cc	Fri Aug 14 22:32:16 2026
--- gcc-15-20260821/gcc/tree-vect-loop-manip.cc	Fri Aug 21 22:32:17 2026
*************** vect_loop_versioning (loop_vec_info loop
*** 4149,4155 ****
  	     && (!loop_outer (loop_to_version)->inner->next
  		 || vect_loop_vectorized_call (loop_to_version))
  	     && (!loop_outer (loop_to_version)->inner->next
! 		 || !loop_outer (loop_to_version)->inner->next->next))
  	loop_to_version = loop_outer (loop_to_version);
      }
  
--- 4149,4156 ----
  	     && (!loop_outer (loop_to_version)->inner->next
  		 || vect_loop_vectorized_call (loop_to_version))
  	     && (!loop_outer (loop_to_version)->inner->next
! 		 || !loop_outer (loop_to_version)->inner->next->next)
! 	     && can_duplicate_loop_p (loop_outer (loop_to_version)))
  	loop_to_version = loop_outer (loop_to_version);
      }
  
diff -Nrcpad gcc-15-20260814/gcc/tree-vect-stmts.cc gcc-15-20260821/gcc/tree-vect-stmts.cc
*** gcc-15-20260814/gcc/tree-vect-stmts.cc	Fri Aug 14 22:32:16 2026
--- gcc-15-20260821/gcc/tree-vect-stmts.cc	Fri Aug 21 22:32:17 2026
*************** vectorizable_store (vec_info *vinfo,
*** 8728,8734 ****
  
    /* Transform.  */
  
!   ensure_base_align (dr_info);
  
    if (STMT_VINFO_SIMD_LANE_ACCESS_P (stmt_info) >= 3)
      {
--- 8728,8735 ----
  
    /* Transform.  */
  
!   if (!costing_p)
!     ensure_base_align (dr_info);
  
    if (STMT_VINFO_SIMD_LANE_ACCESS_P (stmt_info) >= 3)
      {
*************** vectorizable_load (vec_info *vinfo,
*** 10713,10719 ****
    /* Transform.  */
  
    dr_vec_info *dr_info = STMT_VINFO_DR_INFO (stmt_info), *first_dr_info = NULL;
!   ensure_base_align (dr_info);
  
    if (memory_access_type == VMAT_INVARIANT)
      {
--- 10714,10721 ----
    /* Transform.  */
  
    dr_vec_info *dr_info = STMT_VINFO_DR_INFO (stmt_info), *first_dr_info = NULL;
!   if (!costing_p)
!     ensure_base_align (dr_info);
  
    if (memory_access_type == VMAT_INVARIANT)
      {
diff -Nrcpad gcc-15-20260814/libstdc++-v3/ChangeLog gcc-15-20260821/libstdc++-v3/ChangeLog
*** gcc-15-20260814/libstdc++-v3/ChangeLog	Fri Aug 14 22:32:18 2026
--- gcc-15-20260821/libstdc++-v3/ChangeLog	Fri Aug 21 22:32:19 2026
***************
*** 1,3 ****
--- 1,22 ----
+ 2026-08-18  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-07-29  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/126452
+ 	* acinclude.m4 (GLIBCXX_CHECK_LINKER_FEATURES): Use LC_ALL_C and
+ 	match both "Warning" and "warning" in ld output.
+ 	* configure: Regenerate.
+ 
+ 2026-08-17  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-08-17  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/126849
+ 	* include/std/numbers: Fix preprocessor check for
+ 	std::bfloat16_t support.
+ 
  2026-08-01  Jakub Jelinek  <jakub@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260814/libstdc++-v3/acinclude.m4 gcc-15-20260821/libstdc++-v3/acinclude.m4
*** gcc-15-20260814/libstdc++-v3/acinclude.m4	Fri Aug 14 22:32:18 2026
--- gcc-15-20260821/libstdc++-v3/acinclude.m4	Fri Aug 21 22:32:19 2026
*************** AC_DEFUN([GLIBCXX_CHECK_LINKER_FEATURES]
*** 253,260 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 253,260 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[[Ww]]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
diff -Nrcpad gcc-15-20260814/libstdc++-v3/configure gcc-15-20260821/libstdc++-v3/configure
*** gcc-15-20260814/libstdc++-v3/configure	Fri Aug 14 22:32:18 2026
--- gcc-15-20260821/libstdc++-v3/configure	Fri Aug 21 22:32:22 2026
*************** rm -f core conftest.err conftest.$ac_obj
*** 23015,23022 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 23015,23022 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 28882,28889 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 28882,28889 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 32061,32068 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 32061,32068 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 38279,38286 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 38279,38286 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 38567,38574 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 38567,38574 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 39032,39039 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 39032,39039 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 42474,42481 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 42474,42481 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 45869,45876 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 45869,45876 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
*************** rm -f core conftest.err conftest.$ac_obj
*** 46082,46089 ****
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "Warning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
--- 46082,46089 ----
        rm -f conftest.c
        touch conftest.c
        if $CC -c conftest.c; then
! 	if LC_ALL=C $LD --gc-sections -o conftest conftest.o 2>&1 | \
! 	   grep "[Ww]arning: gc-sections option ignored" > /dev/null; then
  	  ac_gcsections=no
  	fi
        fi
diff -Nrcpad gcc-15-20260814/libstdc++-v3/include/std/numbers gcc-15-20260821/libstdc++-v3/include/std/numbers
*** gcc-15-20260814/libstdc++-v3/include/std/numbers	Fri Aug 14 22:32:18 2026
--- gcc-15-20260821/libstdc++-v3/include/std/numbers	Fri Aug 21 22:32:19 2026
*************** __glibcxx_numbers (_Float64, F64);
*** 222,228 ****
  __glibcxx_numbers (_Float128, F128);
  #endif
  
! #ifdef __STDCPP_BFLOAT128_T__
  __glibcxx_numbers (__gnu_cxx::__bfloat16_t, BF16);
  #endif
  
--- 222,228 ----
  __glibcxx_numbers (_Float128, F128);
  #endif
  
! #ifdef __STDCPP_BFLOAT16_T__
  __glibcxx_numbers (__gnu_cxx::__bfloat16_t, BF16);
  #endif
  
